periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 #include "cfg_clock_default.h"
24 #include "cfg_rtc_default.h"
25 #include "cfg_rtt_default.h"
26 #include "cfg_spi_default.h"
27 #include "cfg_timer_default.h"
28 #include "cfg_usbdev_default.h"
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
38 static const uart_conf_t uart_config[] = {
39  {
40  .dev = &SERCOM5->USART,
41  .rx_pin = GPIO_PIN(PB,31), /* D0, RX Pin */
42  .tx_pin = GPIO_PIN(PB,30), /* D1, TX Pin */
43 #ifdef MODULE_PERIPH_UART_HW_FC
44  .rts_pin = GPIO_UNDEF,
45  .cts_pin = GPIO_UNDEF,
46 #endif
47  .mux = GPIO_MUX_D,
48  .rx_pad = UART_PAD_RX_1,
49  .tx_pad = UART_PAD_TX_0_RTS_2_CTS_3,
50  .flags = UART_FLAG_NONE,
51  .gclk_src = SAM0_GCLK_MAIN,
52  },
53  {
54  .dev = &SERCOM4->USART,
55  .rx_pin = GPIO_PIN(PB,13),
56  .tx_pin = GPIO_PIN(PB,14),
57 #ifdef MODULE_PERIPH_UART_HW_FC
58  .rts_pin = GPIO_UNDEF,
59  .cts_pin = GPIO_UNDEF,
60 #endif
61  .mux = GPIO_MUX_C,
62  .rx_pad = UART_PAD_RX_1,
63  .tx_pad = UART_PAD_TX_2,
64  .flags = UART_FLAG_NONE,
65  .gclk_src = SAM0_GCLK_MAIN,
66  },
67  { /* Connected to RN2483 */
68  .dev = &SERCOM0->USART,
69  .rx_pin = GPIO_PIN(PA,5),
70  .tx_pin = GPIO_PIN(PA,6),
71 #ifdef MODULE_PERIPH_UART_HW_FC
72  .rts_pin = GPIO_UNDEF,
73  .cts_pin = GPIO_UNDEF,
74 #endif
75  .mux = GPIO_MUX_D,
76  .rx_pad = UART_PAD_RX_1,
77  .tx_pad = UART_PAD_TX_2,
78  .flags = UART_FLAG_NONE,
79  .gclk_src = SAM0_GCLK_MAIN,
80  },
81 };
82 
83 /* interrupt function name mapping */
84 #define UART_0_ISR isr_sercom5
85 #define UART_1_ISR isr_sercom4
86 #define UART_2_ISR isr_sercom0
87 
88 #define UART_NUMOF ARRAY_SIZE(uart_config)
96 /* ADC Default values */
97 #define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
98 
99 #define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
100 #define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_DIV2
101 #define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
102 
103 static const adc_conf_chan_t adc_channels[] = {
104  /* port, pin, muxpos */
105  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB00 }, /* A0 */
106  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB01 }, /* A1 */
107  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB02 }, /* A2 */
108  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB03 }, /* A3 */
109  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA08 }, /* A4 */
110  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA09 }, /* A5 */
111  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA04 }, /* A6 (temperature) */
112  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA10 }, /* A7 */
113  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA11 }, /* A8 */
114  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB05 }, /* BATVOLT */
115 };
116 
117 #define ADC_NUMOF ARRAY_SIZE(adc_channels)
124 static const i2c_conf_t i2c_config[] = {
125  {
126  .dev = &(SERCOM1->I2CM),
127  .speed = I2C_SPEED_NORMAL,
128  .scl_pin = GPIO_PIN(PA, 17),
129  .sda_pin = GPIO_PIN(PA, 16),
130  .mux = GPIO_MUX_C,
131  .gclk_src = SAM0_GCLK_MAIN,
132  .flags = I2C_FLAG_NONE,
133  },
134  {
135  .dev = &(SERCOM2->I2CM),
136  .speed = I2C_SPEED_NORMAL,
137  .scl_pin = GPIO_PIN(PA, 9),
138  .sda_pin = GPIO_PIN(PA, 8),
139  .mux = GPIO_MUX_C,
140  .gclk_src = SAM0_GCLK_MAIN,
141  .flags = I2C_FLAG_NONE
142  }
143 };
144 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
147 #ifdef __cplusplus
148 }
149 #endif
150 
151 #endif /* PERIPH_CONF_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:69
Default RTC configuration for SODAQ boards.
static const gpio_t adc_channels[]
Static array with declared ADC channels.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:278
@ UART_PAD_RX_1
select pad 1
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0_RTS_2_CTS_3
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
@ UART_PAD_TX_2
select pad 2
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
#define ADC_INPUTCTRL_MUXPOS_PB02
Alias for PIN10.
Definition: periph_cpu.h:129
#define ADC_INPUTCTRL_MUXPOS_PA10
Alias for PIN18.
Definition: periph_cpu.h:137
#define ADC_INPUTCTRL_MUXPOS_PA11
Alias for PIN19.
Definition: periph_cpu.h:138
#define ADC_INPUTCTRL_MUXPOS_PA08
Alias for PIN16.
Definition: periph_cpu.h:135
#define ADC_INPUTCTRL_MUXPOS_PA09
Alias for PIN17.
Definition: periph_cpu.h:136
#define ADC_INPUTCTRL_MUXPOS_PB01
Alias for PIN9.
Definition: periph_cpu.h:128
#define ADC_INPUTCTRL_MUXPOS_PA04
Alias for PIN4.
Definition: periph_cpu.h:123
#define ADC_INPUTCTRL_MUXPOS_PB03
Alias for PIN11.
Definition: periph_cpu.h:130
#define ADC_INPUTCTRL_MUXPOS_PB05
Alias for PIN13.
Definition: periph_cpu.h:132
#define ADC_INPUTCTRL_MUXPOS_PB00
Alias for PIN8.
Definition: periph_cpu.h:127
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition: periph_cpu.h:74
ADC Channel Configuration.
I2C configuration structure.
Definition: periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:300
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219