periph_cpu.h

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/*
 * Copyright (C) 2015-2016 Freie Universität Berlin
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
 
#include <limits.h>
 
#include "periph_cpu_common.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define PM_NUM_MODES        (4)
#ifndef PM_BLOCKER_INITIAL
#define PM_BLOCKER_INITIAL      { 1, 0, 0, 0 }
#endif
 
#define SAMD21_PM_STANDBY       (0U)    
#define SAMD21_PM_IDLE_2        (1U)    
#define SAMD21_PM_IDLE_1        (2U)    
#define SAMD21_PM_IDLE_0        (3U)    
#define SAM0_SPI_PM_BLOCK        SAMD21_PM_IDLE_1 
#define SAM0_USB_ACTIVE_PM_BLOCK SAMD21_PM_IDLE_1 
enum {
    SAM0_GCLK_MAIN = 0,                 
    SAM0_GCLK_1MHZ,                     
    SAM0_GCLK_32KHZ,                    
    SAM0_GCLK_1KHZ,                     
    SAM0_GCLK_DISABLED = 0xF,           
};
#define SPI_HWCS(x)     (UINT_MAX - 1)
 
static inline int _sercom_id(SercomUsart *sercom)
{
    return ((((uint32_t)sercom) >> 10) & 0x7) - 2;
}
 
static const gpio_t sam0_adc_pins[1][20] = {
    {
        GPIO_PIN(PA, 2), GPIO_PIN(PA, 3), GPIO_PIN(PB, 8),  GPIO_PIN(PB, 9),
        GPIO_PIN(PA, 4), GPIO_PIN(PA, 5), GPIO_PIN(PA, 6),  GPIO_PIN(PA, 7),
        GPIO_PIN(PB, 0), GPIO_PIN(PB, 1), GPIO_PIN(PB, 2),  GPIO_PIN(PB, 3),
        GPIO_PIN(PB, 4), GPIO_PIN(PB, 5), GPIO_PIN(PB, 6),  GPIO_PIN(PB, 7),
        GPIO_PIN(PA, 8), GPIO_PIN(PA, 9), GPIO_PIN(PA, 10), GPIO_PIN(PA, 11),
    }
};
 
#define ADC_INPUTCTRL_MUXPOS_PA02 ADC_INPUTCTRL_MUXPOS_PIN0 
#define ADC_INPUTCTRL_MUXPOS_PA03 ADC_INPUTCTRL_MUXPOS_PIN1 
#define ADC_INPUTCTRL_MUXPOS_PB08 ADC_INPUTCTRL_MUXPOS_PIN2 
#define ADC_INPUTCTRL_MUXPOS_PB09 ADC_INPUTCTRL_MUXPOS_PIN3 
#define ADC_INPUTCTRL_MUXPOS_PA04 ADC_INPUTCTRL_MUXPOS_PIN4 
#define ADC_INPUTCTRL_MUXPOS_PA05 ADC_INPUTCTRL_MUXPOS_PIN5 
#define ADC_INPUTCTRL_MUXPOS_PA06 ADC_INPUTCTRL_MUXPOS_PIN6 
#define ADC_INPUTCTRL_MUXPOS_PA07 ADC_INPUTCTRL_MUXPOS_PIN7 
#define ADC_INPUTCTRL_MUXPOS_PB00 ADC_INPUTCTRL_MUXPOS_PIN8 
#define ADC_INPUTCTRL_MUXPOS_PB01 ADC_INPUTCTRL_MUXPOS_PIN9 
#define ADC_INPUTCTRL_MUXPOS_PB02 ADC_INPUTCTRL_MUXPOS_PIN10 
#define ADC_INPUTCTRL_MUXPOS_PB03 ADC_INPUTCTRL_MUXPOS_PIN11 
#define ADC_INPUTCTRL_MUXPOS_PB04 ADC_INPUTCTRL_MUXPOS_PIN12 
#define ADC_INPUTCTRL_MUXPOS_PB05 ADC_INPUTCTRL_MUXPOS_PIN13 
#define ADC_INPUTCTRL_MUXPOS_PB06 ADC_INPUTCTRL_MUXPOS_PIN14 
#define ADC_INPUTCTRL_MUXPOS_PB07 ADC_INPUTCTRL_MUXPOS_PIN15 
#define ADC_INPUTCTRL_MUXPOS_PA08 ADC_INPUTCTRL_MUXPOS_PIN16 
#define ADC_INPUTCTRL_MUXPOS_PA09 ADC_INPUTCTRL_MUXPOS_PIN17 
#define ADC_INPUTCTRL_MUXPOS_PA10 ADC_INPUTCTRL_MUXPOS_PIN18 
#define ADC_INPUTCTRL_MUXPOS_PA11 ADC_INPUTCTRL_MUXPOS_PIN19 
#define ADC_INPUTCTRL_MUXNEG_PA02 ADC_INPUTCTRL_MUXPOS_PIN0 
#define ADC_INPUTCTRL_MUXNEG_PA03 ADC_INPUTCTRL_MUXPOS_PIN1 
#define ADC_INPUTCTRL_MUXNEG_PB08 ADC_INPUTCTRL_MUXPOS_PIN2 
#define ADC_INPUTCTRL_MUXNEG_PB09 ADC_INPUTCTRL_MUXPOS_PIN3 
#define ADC_INPUTCTRL_MUXNEG_PA04 ADC_INPUTCTRL_MUXPOS_PIN4 
#define ADC_INPUTCTRL_MUXNEG_PA05 ADC_INPUTCTRL_MUXPOS_PIN5 
#define ADC_INPUTCTRL_MUXNEG_PA06 ADC_INPUTCTRL_MUXPOS_PIN6 
#define ADC_INPUTCTRL_MUXNEG_PA07 ADC_INPUTCTRL_MUXPOS_PIN7 
#define DAC_RES_BITS        (10)
 
#define DAC_NUMOF           (1)
 
#define RTT_RUNSTDBY        (1)         /* Keep RTT running in sleep states */
 
#define RTT_MAX_VALUE       (0xffffffff)
#define RTT_CLOCK_FREQUENCY (32768U)                      /* in Hz */
#define RTT_MIN_FREQUENCY   (RTT_CLOCK_FREQUENCY / 1024U) /* in Hz */
#define RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY)         /* in Hz */
struct sam0_aux_cfg_mapping {
    uint64_t bootloader_size            :  3; 
    uint64_t reserved_0                 :  1; 
    uint64_t eeprom_size                :  3; 
    uint64_t reserved_1                 :  1; 
    uint64_t bod33_level                :  6; 
    uint64_t bod33_enable               :  1; 
    uint64_t bod33_action               :  2; 
    uint64_t reserved_2                 :  8; 
    uint64_t wdt_enable                 :  1; 
    uint64_t wdt_always_on              :  1; 
    uint64_t wdt_period                 :  4; 
    uint64_t wdt_window                 :  4; 
    uint64_t wdt_ewoffset               :  4; 
    uint64_t wdt_window_enable          :  1; 
    uint64_t bod33_hysteresis           :  1; 
    const uint64_t bod12_calibration    :  1; 
    uint64_t reserved_3                 :  6; 
    uint64_t nvm_locks                  : 16; 
};
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_H */