periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2018 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* Add specific clock configuration (HSE, LSE) for this board here */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 #include "periph_cpu.h"
28 #include "clk_conf.h"
29 #include "cfg_rtt_default.h"
30 #include "cfg_usb_otg_fs.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
40 static const timer_conf_t timer_config[] = {
41  {
42  .dev = TIM5,
43  .max = 0xffffffff,
44  .rcc_mask = RCC_APB1ENR1_TIM5EN,
45  .bus = APB1,
46  .irqn = TIM5_IRQn
47  }
48 };
49 
50 #define TIMER_0_ISR isr_tim5
51 
52 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
59 static const uart_conf_t uart_config[] = {
60  {
61  .dev = USART2,
62  .rcc_mask = RCC_APB1ENR1_USART2EN,
63  .rx_pin = GPIO_PIN(PORT_D, 6),
64  .tx_pin = GPIO_PIN(PORT_D, 5),
65  .rx_af = GPIO_AF7,
66  .tx_af = GPIO_AF7,
67  .bus = APB1,
68  .irqn = USART2_IRQn,
69  .type = STM32_USART,
70  .clk_src = 0, /* Use APB clock */
71 #ifdef UART_USE_DMA
72  .dma_stream = 6,
73  .dma_chan = 4
74 #endif
75  }
76 };
77 
78 #define UART_0_ISR (isr_usart2)
79 
80 #define UART_NUMOF ARRAY_SIZE(uart_config)
112 static const adc_conf_t adc_config[] = {
113  {GPIO_PIN(PORT_A, 0), 0, 5}, /*< ADC12_IN5 */
114  {GPIO_PIN(PORT_A, 5), 0, 10}, /*< ADC12_IN10 */
115  {GPIO_PIN(PORT_A, 1), 0, 6}, /*< ADC12_IN6 */
116  {GPIO_PIN(PORT_A, 2), 0, 7}, /*< ADC12_IN7 */
117  {GPIO_PIN(PORT_A, 3), 0, 8}, /*< ADC12_IN8 */
118  {GPIO_UNDEF, 0, 18}, /* VBAT */
119 };
120 
124 #define VBAT_ADC ADC_LINE(5)
125 
129 #define ADC_NUMOF ARRAY_SIZE(adc_config)
150 static const pwm_conf_t pwm_config[] = {
151  {
152  .dev = TIM2,
153  .rcc_mask = RCC_APB1ENR1_TIM2EN,
154  .chan = { { .pin = GPIO_PIN(PORT_A, 5), .cc_chan = 0},
155  { .pin = GPIO_PIN(PORT_A, 1), .cc_chan = 1},
156  { .pin = GPIO_PIN(PORT_A, 2), .cc_chan = 2},
157  { .pin = GPIO_PIN(PORT_A, 3), .cc_chan = 3} },
158  .af = GPIO_AF1,
159  .bus = APB1
160  },
161  {
162  .dev = TIM1,
163  .rcc_mask = RCC_APB2ENR_TIM1EN,
164  .chan = { { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 1},
165  { .pin = GPIO_PIN(PORT_E, 13), .cc_chan = 2},
166  { .pin = GPIO_PIN(PORT_E, 14), .cc_chan = 3},
167  { .pin = GPIO_UNDEF, .cc_chan = 0} },
168  .af = GPIO_AF1,
169  .bus = APB2
170  }
171 };
172 
173 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
176 #ifdef __cplusplus
177 }
178 #endif
179 
180 #endif /* PERIPH_CONF_H */
@ PORT_E
port E
Definition: periph_cpu.h:51
@ PORT_A
port A
Definition: periph_cpu.h:47
@ PORT_D
port D
Definition: periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:40
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:222
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:112
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:103
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:109
@ STM32_USART
STM32 USART module type.
Definition: cpu_uart.h:38
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:80
ADC device configuration.
Definition: periph_cpu.h:379
PWM device configuration.
mini_timer_t * dev
Timer used.
Timer device configuration.
Definition: periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:265
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219