cc2538_sys_ctrl.h
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1 /*
2  * Copyright (C) 2014 Loci Controls Inc.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef CC2538_SYS_CTRL_H
21 #define CC2538_SYS_CTRL_H
22 
23 #include "cc2538.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
32 typedef struct {
33 
37  union {
38  cc2538_reg_t CLOCK_CTRL;
39  struct {
40  cc2538_reg_t SYS_DIV : 3;
41  cc2538_reg_t RESERVED1 : 5;
42  cc2538_reg_t IO_DIV : 3;
43  cc2538_reg_t RESERVED2 : 5;
44  cc2538_reg_t OSC : 1;
45  cc2538_reg_t OSC_PD : 1;
46  cc2538_reg_t RESERVED3 : 3;
47  cc2538_reg_t AMP_DET : 1;
48  cc2538_reg_t RESERVED4 : 2;
49  cc2538_reg_t OSC32K : 1;
50  cc2538_reg_t OSC32K_CADIS : 1;
51  cc2538_reg_t RESERVED5 : 6;
52  } CLOCK_CTRLbits;
53  } cc2538_sys_ctrl_clk_ctrl;
54 
58  union {
59  cc2538_reg_t CLOCK_STA;
60  struct {
61  cc2538_reg_t SYS_DIV : 3;
62  cc2538_reg_t RESERVED6 : 5;
63  cc2538_reg_t IO_DIV : 3;
64  cc2538_reg_t RESERVED7 : 5;
65  cc2538_reg_t OSC : 1;
66  cc2538_reg_t OSC_PD : 1;
67  cc2538_reg_t HSOSC_STB : 1;
68  cc2538_reg_t XOSC_STB : 1;
69  cc2538_reg_t SOURCE_CHANGE : 1;
70  cc2538_reg_t RESERVED8 : 1;
71  cc2538_reg_t RST : 2;
72  cc2538_reg_t OSC32K : 1;
73  cc2538_reg_t OSC32K_CALDIS : 1;
74  cc2538_reg_t SYNC_32K : 1;
75  cc2538_reg_t RESERVED9 : 5;
76  } CLOCK_STAbits;
77  } cc2538_sys_ctrl_clk_sta;
78 
79  cc2538_reg_t RCGCGPT;
80  cc2538_reg_t SCGCGPT;
81  cc2538_reg_t DCGCGPT;
82  cc2538_reg_t SRGPT;
83  cc2538_reg_t RCGCSSI;
84  cc2538_reg_t SCGCSSI;
85  cc2538_reg_t DCGCSSI;
86  cc2538_reg_t SRSSI;
91  union {
92  cc2538_reg_t RCGCUART;
93  struct {
94  cc2538_reg_t UART0 : 1;
95  cc2538_reg_t UART1 : 1;
96  cc2538_reg_t RESERVED : 30;
97  } RCGCUARTbits;
98  } cc2538_sys_ctrl_unnamed1;
99 
103  union {
104  cc2538_reg_t SCGCUART;
105  struct {
106  cc2538_reg_t UART0 : 1;
107  cc2538_reg_t UART1 : 1;
108  cc2538_reg_t RESERVED : 30;
109  } SCGCUARTbits;
110  } cc2538_sys_ctrl_unnamed2;
111 
115  union {
116  cc2538_reg_t DCGCUART;
117  struct {
118  cc2538_reg_t UART0 : 1;
119  cc2538_reg_t UART1 : 1;
120  cc2538_reg_t RESERVED : 30;
121  } DCGCUARTbits;
122  } cc2538_sys_ctrl_unnamed3;
123 
124  cc2538_reg_t SRUART;
125  cc2538_reg_t RCGCI2C;
126  cc2538_reg_t SCGCI2C;
127  cc2538_reg_t DCGCI2C;
128  cc2538_reg_t SRI2C;
129  cc2538_reg_t RCGCSEC;
130  cc2538_reg_t SCGCSEC;
131  cc2538_reg_t DCGCSEC;
132  cc2538_reg_t SRSEC;
133  cc2538_reg_t PMCTL;
134  cc2538_reg_t SRCRC;
135  cc2538_reg_t RESERVED10[5];
136  cc2538_reg_t PWRDBG;
137  cc2538_reg_t RESERVED11[2];
138  cc2538_reg_t CLD;
139  cc2538_reg_t RESERVED12[4];
140  cc2538_reg_t IWE;
141  cc2538_reg_t I_MAP;
142  cc2538_reg_t RESERVED13[3];
143  cc2538_reg_t RCGCRFC;
144  cc2538_reg_t SCGCRFC;
145  cc2538_reg_t DCGCRFC;
146  cc2538_reg_t EMUOVR;
147 } cc2538_sys_ctrl_t;
148 
149 #define SYS_CTRL ( (cc2538_sys_ctrl_t*)0x400d2000 )
154 #define sys_clock_freq() ((uint32_t)\
155  (SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC ? \
156  RCOSC16M_FREQ : XOSC32M_FREQ) >> \
157  SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.SYS_DIV)
158 
159 #ifdef __cplusplus
160 } /* end extern "C" */
161 #endif
162 
163 #endif /* CC2538_SYS_CTRL_H */
164 
cc2538.h
CC2538 MCU interrupt and register definitions.
cc2538_reg_t
volatile uint32_t cc2538_reg_t
Least-significant 32 bits of the IEEE address.
Definition: cc2538.h:124
UART0
#define UART0
UART0 register bank.
Definition: cc26xx_cc13xx_uart.h:134
UART1
#define UART1
UART1 register bank.
Definition: cc26xx_cc13xx_uart.h:138
cc2538_sys_ctrl_t
System Control component registers.
Definition: cc2538_sys_ctrl.h:32
cc2538_sys_ctrl_t::IO_DIV
cc2538_reg_t IO_DIV
I/O clock rate setting.
Definition: cc2538_sys_ctrl.h:42
cc2538_sys_ctrl_t::PWRDBG
cc2538_reg_t PWRDBG
Power debug register.
Definition: cc2538_sys_ctrl.h:136
cc2538_sys_ctrl_t::IWE
cc2538_reg_t IWE
This register controls interrupt wake-up.
Definition: cc2538_sys_ctrl.h:140
cc2538_sys_ctrl_t::SCGCSSI
cc2538_reg_t SCGCSSI
Module clocks for SSI[1:0] when the CPU is insSleep mode.
Definition: cc2538_sys_ctrl.h:84
cc2538_sys_ctrl_t::RESERVED4
cc2538_reg_t RESERVED4
Reserved bits.
Definition: cc2538_sys_ctrl.h:48
cc2538_sys_ctrl_t::RST
cc2538_reg_t RST
Last source of reset.
Definition: cc2538_sys_ctrl.h:71
cc2538_sys_ctrl_t::SCGCUART
cc2538_reg_t SCGCUART
Module clocks for UART[1:0] when the CPU is in sleep mode.
Definition: cc2538_sys_ctrl.h:104
cc2538_sys_ctrl_t::OSC32K
cc2538_reg_t OSC32K
32-kHz clock oscillator selection
Definition: cc2538_sys_ctrl.h:49
cc2538_sys_ctrl_t::SRGPT
cc2538_reg_t SRGPT
Reset for GPT[3:0].
Definition: cc2538_sys_ctrl.h:82
cc2538_sys_ctrl_t::RCGCSEC
cc2538_reg_t RCGCSEC
Module clocks for the security module when the CPU is in active (run) mode.
Definition: cc2538_sys_ctrl.h:129
cc2538_sys_ctrl_t::SCGCRFC
cc2538_reg_t SCGCRFC
This register defines the module clocks for RF CORE when the CPU is in sleep mode.
Definition: cc2538_sys_ctrl.h:144
cc2538_sys_ctrl_t::RESERVED
cc2538_reg_t RESERVED
Reserved bits.
Definition: cc2538_sys_ctrl.h:96
cc2538_sys_ctrl_t::DCGCSSI
cc2538_reg_t DCGCSSI
Module clocks for SSI[1:0] when the CPU is in PM0.
Definition: cc2538_sys_ctrl.h:85
cc2538_sys_ctrl_t::CLOCK_STA
cc2538_reg_t CLOCK_STA
Clock status register.
Definition: cc2538_sys_ctrl.h:59
cc2538_sys_ctrl_t::RESERVED5
cc2538_reg_t RESERVED5
Reserved bits.
Definition: cc2538_sys_ctrl.h:51
cc2538_sys_ctrl_t::OSC32K_CADIS
cc2538_reg_t OSC32K_CADIS
Disable calibration 32-kHz RC oscillator.
Definition: cc2538_sys_ctrl.h:50
cc2538_sys_ctrl_t::RESERVED7
cc2538_reg_t RESERVED7
Reserved bits.
Definition: cc2538_sys_ctrl.h:64
cc2538_sys_ctrl_t::UART0
cc2538_reg_t UART0
Enable UART0 clock in active (run) mode.
Definition: cc2538_sys_ctrl.h:94
cc2538_sys_ctrl_t::DCGCRFC
cc2538_reg_t DCGCRFC
This register defines the module clocks for RF CORE when the CPU is in PM0.
Definition: cc2538_sys_ctrl.h:145
cc2538_sys_ctrl_t::EMUOVR
cc2538_reg_t EMUOVR
This register defines the emulator override controls for power mode and peripheral clock gate.
Definition: cc2538_sys_ctrl.h:146
cc2538_sys_ctrl_t::SCGCGPT
cc2538_reg_t SCGCGPT
Module clocks for GPT[3:0] when the CPU is in sleep mode.
Definition: cc2538_sys_ctrl.h:80
cc2538_sys_ctrl_t::AMP_DET
cc2538_reg_t AMP_DET
Amplitude detector of XOSC during power up.
Definition: cc2538_sys_ctrl.h:47
cc2538_sys_ctrl_t::HSOSC_STB
cc2538_reg_t HSOSC_STB
HSOSC stable status.
Definition: cc2538_sys_ctrl.h:67
cc2538_sys_ctrl_t::SRSSI
cc2538_reg_t SRSSI
Reset for SSI[1:0].
Definition: cc2538_sys_ctrl.h:86
cc2538_sys_ctrl_t::SRI2C
cc2538_reg_t SRI2C
Reset for I2C.
Definition: cc2538_sys_ctrl.h:128
cc2538_sys_ctrl_t::RCGCRFC
cc2538_reg_t RCGCRFC
This register defines the module clocks for RF CORE when the CPU is in active (run) mode.
Definition: cc2538_sys_ctrl.h:143
cc2538_sys_ctrl_t::RESERVED6
cc2538_reg_t RESERVED6
Reserved bits.
Definition: cc2538_sys_ctrl.h:62
cc2538_sys_ctrl_t::RESERVED8
cc2538_reg_t RESERVED8
Reserved bits.
Definition: cc2538_sys_ctrl.h:70
cc2538_sys_ctrl_t::CLD
cc2538_reg_t CLD
This register controls the clock loss detection feature.
Definition: cc2538_sys_ctrl.h:138
cc2538_sys_ctrl_t::RCGCSSI
cc2538_reg_t RCGCSSI
Module clocks for SSI[1:0] when the CPU is in active (run) mode.
Definition: cc2538_sys_ctrl.h:83
cc2538_sys_ctrl_t::DCGCUART
cc2538_reg_t DCGCUART
Module clocks for UART[1:0] when the CPU is in PM0.
Definition: cc2538_sys_ctrl.h:116
cc2538_sys_ctrl_t::SYNC_32K
cc2538_reg_t SYNC_32K
32-kHz clock source synced to undivided system clock (16 or 32 MHz)
Definition: cc2538_sys_ctrl.h:74
cc2538_sys_ctrl_t::PMCTL
cc2538_reg_t PMCTL
Power mode.
Definition: cc2538_sys_ctrl.h:133
cc2538_sys_ctrl_t::SRUART
cc2538_reg_t SRUART
Reset for UART[1:0].
Definition: cc2538_sys_ctrl.h:124
cc2538_sys_ctrl_t::DCGCI2C
cc2538_reg_t DCGCI2C
Module clocks for I2C when the CPU is in PM0.
Definition: cc2538_sys_ctrl.h:127
cc2538_sys_ctrl_t::RCGCGPT
cc2538_reg_t RCGCGPT
Module clocks for GPT[3:0] when the CPU is in active (run) mode.
Definition: cc2538_sys_ctrl.h:79
cc2538_sys_ctrl_t::RESERVED1
cc2538_reg_t RESERVED1
Reserved bits.
Definition: cc2538_sys_ctrl.h:41
cc2538_sys_ctrl_t::SOURCE_CHANGE
cc2538_reg_t SOURCE_CHANGE
System clock source change.
Definition: cc2538_sys_ctrl.h:69
cc2538_sys_ctrl_t::RESERVED2
cc2538_reg_t RESERVED2
Reserved bits.
Definition: cc2538_sys_ctrl.h:43
cc2538_sys_ctrl_t::DCGCGPT
cc2538_reg_t DCGCGPT
Module clocks for GPT[3:0] when the CPU is in PM0.
Definition: cc2538_sys_ctrl.h:81
cc2538_sys_ctrl_t::SCGCI2C
cc2538_reg_t SCGCI2C
Module clocks for I2C when the CPU is in sleep mode.
Definition: cc2538_sys_ctrl.h:126
cc2538_sys_ctrl_t::CLOCK_CTRL
cc2538_reg_t CLOCK_CTRL
Clock control register.
Definition: cc2538_sys_ctrl.h:38
cc2538_sys_ctrl_t::SCGCSEC
cc2538_reg_t SCGCSEC
Module clocks for the security module when the CPU is in sleep mode.
Definition: cc2538_sys_ctrl.h:130
cc2538_sys_ctrl_t::RESERVED9
cc2538_reg_t RESERVED9
Reserved bits.
Definition: cc2538_sys_ctrl.h:75
cc2538_sys_ctrl_t::OSC32K_CALDIS
cc2538_reg_t OSC32K_CALDIS
Disable calibration 32-kHz RC oscillator.
Definition: cc2538_sys_ctrl.h:73
cc2538_sys_ctrl_t::DCGCSEC
cc2538_reg_t DCGCSEC
Module clocks for the security module when the CPU is in PM0.
Definition: cc2538_sys_ctrl.h:131
cc2538_sys_ctrl_t::XOSC_STB
cc2538_reg_t XOSC_STB
XOSC stable status.
Definition: cc2538_sys_ctrl.h:68
cc2538_sys_ctrl_t::I_MAP
cc2538_reg_t I_MAP
This register selects which interrupt map to be used.
Definition: cc2538_sys_ctrl.h:141
cc2538_sys_ctrl_t::OSC_PD
cc2538_reg_t OSC_PD
Oscillator power-down.
Definition: cc2538_sys_ctrl.h:45
cc2538_sys_ctrl_t::RESERVED3
cc2538_reg_t RESERVED3
Reserved bits.
Definition: cc2538_sys_ctrl.h:46
cc2538_sys_ctrl_t::UART1
cc2538_reg_t UART1
Enable UART1 clock in active (run) mode.
Definition: cc2538_sys_ctrl.h:95
cc2538_sys_ctrl_t::SYS_DIV
cc2538_reg_t SYS_DIV
System clock rate setting.
Definition: cc2538_sys_ctrl.h:40
cc2538_sys_ctrl_t::OSC
cc2538_reg_t OSC
System clock oscillator selection.
Definition: cc2538_sys_ctrl.h:44
cc2538_sys_ctrl_t::SRSEC
cc2538_reg_t SRSEC
Reset for the security module.
Definition: cc2538_sys_ctrl.h:132
cc2538_sys_ctrl_t::RCGCUART
cc2538_reg_t RCGCUART
Module clocks for UART[1:0] when the CPU is in active (run) mode.
Definition: cc2538_sys_ctrl.h:92
cc2538_sys_ctrl_t::RCGCI2C
cc2538_reg_t RCGCI2C
Module clocks for I2C when the CPU is in active (run) mode.
Definition: cc2538_sys_ctrl.h:125
cc2538_sys_ctrl_t::SRCRC
cc2538_reg_t SRCRC
CRC on state retention.
Definition: cc2538_sys_ctrl.h:134