cfg_usb_otg_hs_phy_fs.h
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1 /*
2  * Copyright (C) 2019 Koen Zandberg
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
23 #ifndef CFG_USB_OTG_HS_PHY_FS_H
24 #define CFG_USB_OTG_HS_PHY_FS_H
25 
26 #include "periph_cpu.h"
27 #include "usbdev_synopsys_dwc2.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
36 #define DWC2_USB_OTG_HS_ENABLED
37 
41 static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = {
42  {
43  .periph = USB_OTG_HS_PERIPH_BASE,
44  .type = DWC2_USB_OTG_HS,
45  .phy = DWC2_USB_OTG_PHY_BUILTIN,
46  .rcc_mask = RCC_AHB1ENR_OTGHSEN,
47  .irqn = OTG_HS_IRQn,
48  .ahb = AHB1,
49  .dm = GPIO_PIN(PORT_B, 14),
50  .dp = GPIO_PIN(PORT_B, 15),
51  .af = GPIO_AF12,
52  }
53 };
54 
58 #define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
59 
60 #ifdef __cplusplus
61 }
62 #endif
63 
64 #endif /* CFG_USB_OTG_HS_PHY_FS_H */
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:48
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
dwc2_usb_otg_fshs_config
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG FS configuration.
Definition: cfg_usb_otg_hs_phy_fs.h:41
GPIO_AF12
@ GPIO_AF12
use alternate function 12
Definition: cpu_gpio.h:115
dwc2_usb_otg_fshs_config_t
USB OTG configuration.
Definition: usbdev_synopsys_dwc2.h:80
dwc2_usb_otg_fshs_config_t::periph
uintptr_t periph
USB peripheral base address.
Definition: usbdev_synopsys_dwc2.h:81
usbdev_synopsys_dwc2.h
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
DWC2_USB_OTG_PHY_BUILTIN
@ DWC2_USB_OTG_PHY_BUILTIN
on-chip FS PHY
Definition: usbdev_synopsys_dwc2.h:72
DWC2_USB_OTG_HS
@ DWC2_USB_OTG_HS
High speed peripheral.
Definition: usbdev_synopsys_dwc2.h:49