CMSIS Definitions

Detailed Description

Macros
#define	RCOSC48M_FREQ   48000000
	48 MHz
#define	RCOSC24M_FREQ   24000000
	24 MHz
enum	IRQn {   ResetHandler_IRQn = -15 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 ,   BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = - 5 , DebugMonitor_IRQn = - 4 ,   PendSV_IRQn = - 2 , SysTick_IRQn = - 1 , GPIO_PORT_A_IRQn = 0 , GPIO_PORT_B_IRQn = 1 ,   GPIO_PORT_C_IRQn = 2 , GPIO_PORT_D_IRQn = 3 , UART0_IRQn = 5 , UART1_IRQn = 6 ,   SSI0_IRQn = 7 , I2C_IRQn = 8 , ADC_IRQn = 14 , WDT_IRQn = 18 ,   GPTIMER_0A_IRQn = 19 , GPTIMER_0B_IRQn = 20 , GPTIMER_1A_IRQn = 21 , GPTIMER_1B_IRQn = 22 ,   GPTIMER_2A_IRQn = 23 , GPTIMER_2B_IRQn = 24 , ADC_CMP_IRQn = 25 , RF_RXTX_ALT_IRQn = 26 ,   RF_ERR_ALT_IRQn = 27 , SYS_CTRL_IRQn = 28 , FLASH_CTRL_IRQn = 29 , AES_ALT_IRQn = 30 ,   PKA_ALT_IRQn = 31 , SM_TIMER_ALT_IRQn = 32 , MAC_TIMER_ALT_IRQn = 33 , SSI1_IRQn = 34 ,   GPTIMER_3A_IRQn = 35 , GPTIMER_3B_IRQn = 36 , UDMA_IRQn = 46 , UDMA_ERR_IRQn = 47 ,   USB_IRQn = 140 , RF_RXTX_IRQn = 141 , RF_ERR_IRQn = 142 , AES_IRQn = 143 ,   PKA_IRQn = 144 , SM_TIMER_IRQn = 145 , MACTIMER_IRQn = 146 , PERIPH_COUNT_IRQn = (MACTIMER_IRQn + 1) ,   ResetHandler_IRQn = -15 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 ,   BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = - 5 , DebugMonitor_IRQn = - 4 ,   PendSV_IRQn = - 2 , SysTick_IRQn = - 1 , EDGE_DETECT_IRQN = 0 , I2C_IRQN = 1 ,   RF_CPE1_IRQN = 2 , PKA_IRQN = 3 , AON_RTC_IRQN = 4 , UART0_IRQN = 5 ,   AON_AUX_SWEV0_IRQN = 6 , SSI0_IRQN = 7 , SSI1_IRQN = 8 , RF_CPE0_IRQN = 9 ,   RF_HW_IRQN = 10 , RF_CMD_ACK_IRQN = 11 , I2S_IRQN = 12 , AON_AUX_SWEV1_IRQN = 13 ,   WATCHDOG_IRQN = 14 , GPTIMER_0A_IRQN = 15 , GPTIMER_0B_IRQN = 16 , GPTIMER_1A_IRQN = 17 ,   GPTIMER_1B_IRQN = 18 , GPTIMER_2A_IRQN = 19 , GPTIMER_2B_IRQN = 20 , GPTIMER_3A_IRQN = 21 ,   GPTIMER_3B_IRQN = 22 , CRYPTO_IRQN = 23 , UDMA_IRQN = 24 , UDMA_ERR_IRQN = 25 ,   FLASH_CTRL_IRQN = 26 , SW0_IRQN = 27 , AUX_COMBO_IRQN = 28 , AON_PRG0_IRQN = 29 ,   PROG_IRQN = 30 , AUX_COMPA_IRQN = 31 , AUX_ADC_IRQN = 32 , TRNG_IRQN = 33 ,   IRQN_COUNT = (TRNG_IRQN + 1) }
	Interrupt number definition. More...
typedef enum IRQn	IRQn_Type
	Interrupt number definition.
typedef volatile uint8_t	reg8_t
	Unsigned 8-bit register type.
typedef volatile uint16_t	reg16_t
	Unsigned 16-bit register type.
typedef volatile uint32_t	reg32_t
	Unsigned 32-bit register type.
typedef reg16_t	reg8_m8_t
	Masked 8-bit register.
#define	__MPU_PRESENT   1
	Configuration of the Cortex-M4 processor and core peripherals. More...
#define	__NVIC_PRIO_BITS   3
	CC13x2 offers priority levels from 0..7.
#define	__Vendor_SysTickConfig   0
	Set to 1 if different SysTick config is used.

Macro Definition Documentation

__MPU_PRESENT

#define __MPU_PRESENT   1

Configuration of the Cortex-M4 processor and core peripherals.

CC13x2 does provide a MPU

Definition at line 135 of file cc26xx_cc13xx.h.

Enumeration Type Documentation

IRQn

enum IRQn

Interrupt number definition.

Enumerator
ResetHandler_IRQn	1 Reset Handler
NonMaskableInt_IRQn	2 Non Maskable Interrupt
HardFault_IRQn	3 Cortex-M3 Hard Fault Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
GPIO_PORT_A_IRQn	GPIO port A
GPIO_PORT_B_IRQn	GPIO port B
GPIO_PORT_C_IRQn	GPIO port C
GPIO_PORT_D_IRQn	GPIO port D
UART0_IRQn	UART0
UART1_IRQn	UART1
SSI0_IRQn	SSI0
I2C_IRQn	I2C
ADC_IRQn	ADC
WDT_IRQn	Watchdog Timer
GPTIMER_0A_IRQn	GPTimer 0A
GPTIMER_0B_IRQn	GPTimer 0B
GPTIMER_1A_IRQn	GPTimer 1A
GPTIMER_1B_IRQn	GPTimer 1B
GPTIMER_2A_IRQn	GPTimer 2A
GPTIMER_2B_IRQn	GPTimer 2B
ADC_CMP_IRQn	Analog Comparator
RF_RXTX_ALT_IRQn	RF TX/RX (Alternate)
RF_ERR_ALT_IRQn	RF Error (Alternate)
SYS_CTRL_IRQn	System Control
FLASH_CTRL_IRQn	Flash memory control
AES_ALT_IRQn	AES (Alternate)
PKA_ALT_IRQn	PKA (Alternate)
SM_TIMER_ALT_IRQn	SM Timer (Alternate)
MAC_TIMER_ALT_IRQn	MAC Timer (Alternate)
SSI1_IRQn	SSI1
GPTIMER_3A_IRQn	GPTimer 3A
GPTIMER_3B_IRQn	GPTimer 3B
UDMA_IRQn	uDMA software
UDMA_ERR_IRQn	uDMA error
USB_IRQn	USB
RF_RXTX_IRQn	RF Core Rx/Tx
RF_ERR_IRQn	RF Core Error
AES_IRQn	AES
PKA_IRQn	PKA
SM_TIMER_IRQn	SM Timer
MACTIMER_IRQn	MAC Timer
PERIPH_COUNT_IRQn	Number of peripheral IDs.
ResetHandler_IRQn	1 Reset Handler
NonMaskableInt_IRQn	2 Non Maskable Interrupt
HardFault_IRQn	3 Cortex-M4 Hard Fault Interrupt
MemoryManagement_IRQn	4 Cortex-M4 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M4 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M4 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M4 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M4 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M4 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M4 System Tick Interrupt
EDGE_DETECT_IRQN	16 AON edge detect
I2C_IRQN	17 I2C
RF_CPE1_IRQN	18 RF Command and Packet Engine 1
PKA_IRQN	19 PKA interrupt
AON_RTC_IRQN	20 AON RTC
UART0_IRQN	21 UART0 Rx and Tx
AON_AUX_SWEV0_IRQN	22 Sensor Controller software event 0, through AON domain
SSI0_IRQN	23 SSI0 Rx and Tx
SSI1_IRQN	24 SSI1 Rx and Tx
RF_CPE0_IRQN	25 RF Command and Packet Engine 0
RF_HW_IRQN	26 RF Core Hardware
RF_CMD_ACK_IRQN	27 RF Core Command Acknowledge
I2S_IRQN	28 I2S
AON_AUX_SWEV1_IRQN	29 Sensor Controller software event 1, through AON domain
WATCHDOG_IRQN	30 Watchdog timer
GPTIMER_0A_IRQN	31 Timer 0 subtimer A
GPTIMER_0B_IRQN	32 Timer 0 subtimer B
GPTIMER_1A_IRQN	33 Timer 1 subtimer A
GPTIMER_1B_IRQN	34 Timer 1 subtimer B
GPTIMER_2A_IRQN	35 Timer 2 subtimer A
GPTIMER_2B_IRQN	36 Timer 2 subtimer B
GPTIMER_3A_IRQN	37 Timer 3 subtimer A
GPTIMER_3B_IRQN	38 Timer 3 subtimer B
CRYPTO_IRQN	39 Crypto Core Result available
UDMA_IRQN	40 uDMA Software
UDMA_ERR_IRQN	41 uDMA Error
FLASH_CTRL_IRQN	42 Flash controller
SW0_IRQN	43 Software Event 0
AUX_COMBO_IRQN	44 AUX combined event, directly to MCU domain
AON_PRG0_IRQN	45 AON programmable 0
PROG_IRQN	46 Dynamic Programmable interrupt (default source: PRCM)
AUX_COMPA_IRQN	47 AUX Comparator A
AUX_ADC_IRQN	48 AUX ADC IRQ
TRNG_IRQN	49 TRNG event
IRQN_COUNT	Number of peripheral IDs.

Definition at line 70 of file cc26xx_cc13xx.h.