Common implementations and headers for the RISC-V CPU. More...

Detailed Description

Common implementations and headers for the RISC-V CPU.

Files
file	clic.h
	RISCV CLIC interrupt controller definitions.

file	context_frame.h
	Thread context frame stored on stack.

file	cpu_common.h
	Basic definitions for the RISC-V CPU module.

file	cpu_conf_common.h
	RISC-V CPU configuration options.

file	cpucycle.h
	Functions to read CPU cycle counter.

file	irq_arch.h
	Implementation of the kernels irq interface.

file	periph_cpu_common.h
	CPU specific definitions for internal peripheral handling.

file	plic.h
	Platform-Level interrupt controller driver.

file	pmp.h
	RISC-V PMP configuration options.

Functions
void	riscv_init (void)
	Initialize rv32i specific core parts of the CPU. More...

void	riscv_fpu_init (void)
	Enable the rv32i FPU when present.

void	riscv_irq_init (void)
	Initialization of the interrupt controller.

static uintptr_t	cpu_get_caller_pc (void)
	Gets the last instruction's address. More...

static void	cpu_reg_enable_bits (volatile uint32_t *reg, uint32_t mask)
	Convenience function to set bit flags in a register. More...

static void	cpu_reg_disable_bits (volatile uint32_t *reg, uint32_t mask)
	Convenience function to clear bit flags in a register. More...

Function Documentation

static uintptr_t cpu_get_caller_pc ( void )

inlinestatic

Gets the last instruction's address.

Definition at line 54 of file cpu_common.h.

static void cpu_reg_disable_bits	(	volatile uint32_t *	reg,
		uint32_t	mask
	)

inlinestatic

Convenience function to clear bit flags in a register.

Parameters

reg	register to clear bits in
mask	bits to clear in the register

Definition at line 79 of file cpu_common.h.

static void cpu_reg_enable_bits	(	volatile uint32_t *	reg,
		uint32_t	mask
	)

inlinestatic

Convenience function to set bit flags in a register.

Parameters

reg	register to set bits in
mask	bits to set in the register

Definition at line 67 of file cpu_common.h.

void riscv_init ( void )

Initialize rv32i specific core parts of the CPU.

Initialized the interrupt controller and the enables the FPU if present