lis2dh12_registers.h
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1 /*
2  * Copyright (C) 2021 ML!PA Consulting GmbH
3  *
4  */
5 
16 #ifndef LIS2DH12_REGISTERS_H
17 #define LIS2DH12_REGISTERS_H
18 
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22 
31 enum {
34 };
35 
39 enum {
42 };
43 
47 enum {
56 };
57 
61 enum {
68  LIS2DH12_INT_SRC_IA = 0x40,
70 };
71 
75 enum {
84 };
85 
89 enum {
90  /* for interrupt 1 (CTRL_REG3) */
98  /* for interrupt 2 (CTRL_REG6) */
109 };
110 
114 enum {
118 };
119 
123 #define LIS2DH12_INT_SRC_1(ret) (((uint32_t)(ret) >> 0) & 0x7F)
124 
128 #define LIS2DH12_INT_SRC_2(ret) (((uint32_t)(ret) >> 8) & 0x7F)
129 
133 #define LIS2DH12_INT_SRC_CLICK(ret) (((uint32_t)(ret) >> 16) & 0x7F)
134 
138 typedef union {
139  struct {
140  uint8_t X_AXIS:1;
141  uint8_t Y_AXIS:1;
142  uint8_t Z_AXIS:1;
143  uint8_t Sign:1;
144  uint8_t SClick:1;
145  uint8_t DClick:1;
146  uint8_t IA:1;
148  uint8_t _RESERVED:1;
149  } bit;
150  uint8_t reg;
152 
156 typedef union {
157  struct {
158  uint8_t FSS:5;
159  uint8_t EMPTY:1;
160  uint8_t OVRN_FIFO:1;
161  uint8_t WTM:1;
162  } bit;
163  uint8_t reg;
175 typedef union {
176  struct {
178  uint8_t SDO_PU_DISC:1;
179  } bit;
180  uint8_t reg;
182 
186 typedef union {
187  struct {
188  uint8_t _RESERVED:6;
189  uint8_t TEMP_EN:2;
190  } bit;
191  uint8_t reg;
193 
197 typedef union {
198  struct {
199  uint8_t Xen:1;
200  uint8_t Yen:1;
201  uint8_t Zen:1;
202  uint8_t LPen:1;
203  uint8_t ODR:4;
204  } bit;
205  uint8_t reg;
207 
208 #define LIS2DH12_CTRL_REG2_HP_IA1 (1 << 0)
209 #define LIS2DH12_CTRL_REG2_HP_IA2 (1 << 1)
210 #define LIS2DH12_CTRL_REG2_HPCLICK (1 << 2)
211 #define LIS2DH12_CTRL_REG2_FDS (1 << 3)
212 
213 #define LIS2DH12_CLICK_THS_LIR (0x80)
214 
218 typedef union {
219  struct {
220  uint8_t HP_IA1:1;
221  uint8_t HP_IA2:1;
222  uint8_t HPCLICK:1;
223  uint8_t FDS:1;
224  uint8_t HPCF:2;
225  uint8_t HPM:2;
226  } bit;
227  uint8_t reg;
229 
233 typedef union {
234  struct {
235  uint8_t _RESERVED0:1;
236  uint8_t I1_OVERRUN:1;
237  uint8_t I1_WTM:1;
238  uint8_t _RESERVED3:1;
239  uint8_t I1_ZYXDA:1;
240  uint8_t I1_IA2:1;
241  uint8_t I1_IA1:1;
242  uint8_t I1_CLICK:1;
243  } bit;
244  uint8_t reg;
246 
250 typedef union {
251  struct {
252  uint8_t SPIM:1;
253  uint8_t ST:2;
254  uint8_t HR:1;
255  uint8_t FS:2;
256  uint8_t BLE:1;
257  uint8_t BDU:1;
258  } bit;
259  uint8_t reg;
261 
265 typedef union {
266  struct {
267  uint8_t D4D_INT2:1;
268  uint8_t LIR_INT2:1;
269  uint8_t D4D_INT1:1;
270  uint8_t LIR_INT1:1;
271  uint8_t _RESERVED:2;
272  uint8_t FIFO_EN:1;
273  uint8_t BOOT:1;
274  } bit;
275  uint8_t reg;
277 
281 typedef union {
282  struct {
283  uint8_t _RESERVED0:1;
284  uint8_t INT_POLARITY:1;
285  uint8_t _RESERVED2:1;
286  uint8_t I2_ACT:1;
287  uint8_t I2_BOOT:1;
288  uint8_t I2_IA2:1;
289  uint8_t I2_IA1:1;
290  uint8_t I2_CLICK:1;
291  } bit;
292  uint8_t reg;
294 
298 typedef union {
299  uint8_t reg;
301 
305 typedef union {
306  struct {
307  uint8_t FTH:5;
308  uint8_t TR:1;
309  uint8_t FM:2;
310  } bit;
311  uint8_t reg;
313 
317 typedef union {
318  struct {
319  uint8_t XLIE:1;
320  uint8_t XHIE:1;
321  uint8_t YLIE:1;
322  uint8_t YHIE:1;
323  uint8_t ZLIE:1;
324  uint8_t ZHIE:1;
325  uint8_t D6D:1;
326  uint8_t AOI:1;
327  } bit;
328  uint8_t reg;
330 
334 typedef union {
335  struct {
336  uint8_t THS:7;
339  uint8_t _RESERVED:1;
340  } bit;
341  uint8_t reg;
343 
347 typedef union {
348  struct {
349  uint8_t D:7;
350  uint8_t _RESERVED:1;
351  } bit;
352  uint8_t reg;
354 
358 typedef union {
359  struct {
360  uint8_t XLIE:1;
361  uint8_t XHIE:1;
362  uint8_t YLIE:1;
363  uint8_t YHIE:1;
364  uint8_t ZLIE:1;
365  uint8_t ZHIE:1;
366  uint8_t D6D:1;
367  uint8_t AOI:1;
368  } bit;
369  uint8_t reg;
371 
375 typedef union {
376  struct {
377  uint8_t THS:7;
378  uint8_t _RESERVED:1;
379  } bit;
380  uint8_t reg;
382 
386 typedef union {
387  struct {
388  uint8_t D:7;
389  uint8_t _RESERVED:1;
390  } bit;
391  uint8_t reg;
393 
397 typedef union {
398  struct {
399  uint8_t XS:1;
400  uint8_t XD:1;
401  uint8_t YS:1;
402  uint8_t YD:1;
403  uint8_t ZS:1;
404  uint8_t ZD:1;
405  uint8_t _RESERVED:2;
406  } bit;
407  uint8_t reg;
409 
413 typedef union {
414  struct {
415  uint8_t THS:7;
416  uint8_t LIR_CLICK:1;
419  } bit;
420  uint8_t reg;
422 
426 typedef union {
427  struct {
428  uint8_t TLI:7;
429  uint8_t _RESERVED:1;
430  } bit;
431  uint8_t reg;
433 
437 typedef union {
438  uint8_t reg;
440 
444 typedef union {
445  uint8_t reg;
447 
451 typedef union {
452  struct {
453  uint8_t ACTH:7;
455  uint8_t _RESERVED:1;
456  } bit;
457  uint8_t reg;
459 
463 typedef union {
464  uint8_t reg;
468 #ifdef __cplusplus
469 }
470 #endif
471 
472 #endif /* LIS2DH12_REGISTERS_H */
@ LIS2DH12_STATUS_REG_ZYXDA
On X-, Y-, Z-axis new data available.
@ LIS2DH12_STATUS_REG_YOR
Y-axis data overrun.
@ LIS2DH12_STATUS_REG_XOR
X-axis data overrun.
@ LIS2DH12_STATUS_REG_ZOR
Y-axis data overrun.
@ LIS2DH12_STATUS_REG_YDA
Y-axis new data available.
@ LIS2DH12_STATUS_REG_XDA
X-axis new data available.
@ LIS2DH12_STATUS_REG_ZDA
Z-axis new data available.
@ LIS2DH12_STATUS_REG_ZYXOR
On X-, Y-, Z-axis data overrun.
@ LIS2DH12_INT_CFG_ZHIE
enable Z high event
@ LIS2DH12_INT_CFG_YHIE
enable Y high event
@ LIS2DH12_INT_CFG_XLIE
enable X low event
@ LIS2DH12_INT_CFG_6D
enable 6-direction detection
@ LIS2DH12_INT_CFG_XHIE
enable X high event
@ LIS2DH12_INT_CFG_ZLIE
enable Z low event
@ LIS2DH12_INT_CFG_YLIE
enable Y low event
@ LIS2DH12_INT_CFG_AOI
and/or combination interrupt events
@ LIS2DH12_STATUS_REG_AUX_TOR
Temperature data overrun.
@ LIS2DH12_STATUS_REG_AUX_TDA
Temperature new data available.
@ LIS2DH12_INT_SRC_XL
X low event.
@ LIS2DH12_INT_SRC_XH
X high event.
@ LIS2DH12_INT_SRC_ZL
Z low event.
@ LIS2DH12_INT_SRC_ZH
Z high event.
@ LIS2DH12_INT_SRC_YL
Y low event.
@ LIS2DH12_INT_SRC_IA
Interrupt 1 active, at least one interrupt \ has been generated.
@ LIS2DH12_INT_SRC_YH
Y high event.
@ LIS2DH12_INT_TYPE_I1_WTM
FIFO watermark interrupt on INT1.
@ LIS2DH12_INT_TYPE_I1_ZYXDA
ZYXDA interrupt on INT1.
@ LIS2DH12_INT_TYPE_I2_IA2
IA2 on INT2.
@ LIS2DH12_INT_TYPE_I2_ACT
enable activity interrupt on INT2
@ LIS2DH12_INT_TYPE_I2_CLICK
click interrupt on INT2
@ LIS2DH12_INT_TYPE_CLICK
click interrupt
@ LIS2DH12_INT_TYPE_IA2
Event 2.
@ LIS2DH12_INT_TYPE_I2_IA1
IA1 on INT2.
@ LIS2DH12_INT_TYPE_I1_IA2
IA2 interrupt on INT1.
@ LIS2DH12_INT_TYPE_IA1
Event 1.
@ LIS2DH12_INT_TYPE_I2_BOOT
enable boot on INT2
@ LIS2DH12_INT_TYPE_I1_OVERRUN
FIFO overrun interrupt on INT1.
@ LIS2DH12_INT_TYPE_I1_IA1
IA1 interrupt on INT1.
@ LIS2DH12_INT_TYPE_INT_POLARITY
INT1 and INT2 pin polarity.
@ LIS2DH12_INT_TYPE_I1_CLICK
click interrupt on INT1
@ LIS2DH12_EVENT_2
second event slot
@ LIS2DH12_EVENT_1
first event slot
@ LIS2DH12_EVENT_CLICK
click event
@ LIS2DH12_TEMP_CFG_REG_DISABLE
Temperature sensor disable.
@ LIS2DH12_TEMP_CFG_REG_ENABLE
Temperature sensor enable
ACT_DURATION definitions.
uint8_t reg
Sleep-to-wake and return-to-sleep duration, in ODR cycles.
ACT_THS definitions.
uint8_t ACTH
Sets the threshold sleep-to-wake or return-to-sleep LSB according to LIS2DH12_SCALE.
uint8_t _RESERVED
reserved bit
uint8_t reg
Type used for register access.
CLICK_CFG definitions.
uint8_t _RESERVED
Reserved bits.
uint8_t XD
Interrupt double-click enable on X-axis.
uint8_t ZS
Interrupt single-click enable on Z-axis.
uint8_t reg
Type used for register access.
uint8_t YD
Interrupt double-click enable on Y-axis.
uint8_t YS
Interrupt single-click enable on Y-axis.
uint8_t ZD
Interrupt double-click enable on Z-axis.
uint8_t XS
Interrupt single-click enable on X-axis.
CLICK_SRC definitions.
uint8_t SClick
Single click detected.
uint8_t _RESERVED
Reserved bit.
uint8_t X_AXIS
X click detected.
uint8_t Z_AXIS
Z click detected.
uint8_t Y_AXIS
Y click detected.
uint8_t DClick
Double click detected.
uint8_t reg
Type used for register access.
uint8_t IA
Interrupt active, at least one interrupt \ has been generated.
uint8_t Sign
Click sign, "0" positive, "1" negative.
CLICK_THS definitions.
uint8_t reg
Type used for register access.
uint8_t LIR_CLICK
Enables latency on interrupt kept high, \ "0" for duration of latency window, \ "1" kept high until C...
uint8_t THS
Sets the click threshold, LSB according to LIS2DH12_SCALE.
CTRL_REG_0 definitions.
uint8_t CTRL0_DEFAULT_VALUE
Always set this to CTRL_REG0_DEFAULT.
uint8_t reg
Type used for register access.
uint8_t SDO_PU_DISC
disconnect pull-up on SDO/SA0
CTRL_REG1 definitions.
uint8_t Xen
X axis enable.
uint8_t reg
Type used for register access.
uint8_t ODR
Set Data rate.
uint8_t Zen
Z axis enable.
uint8_t Yen
Y axis enable.
uint8_t LPen
Enable Low Power mode.
CTRL_REG2 definitions.
uint8_t HPCLICK
High pass filter enable for CLICK function.
uint8_t HP_IA2
High pass filter enable for AOI on interrupt 2.
uint8_t HPCF
High pass filter cutoff frequency.
uint8_t HPM
High pass filter mode selection.
uint8_t reg
Type used for register access.
uint8_t HP_IA1
High pass filter enable for AOI on interrupt 1.
uint8_t FDS
Enables filter output data.
CTRL_REG3 definitions.
uint8_t I1_IA2
Enable IA2 interrupt on INT1.
uint8_t I1_OVERRUN
Enable FIFO overrun interrupt on INT1.
uint8_t _RESERVED3
Should always be "0".
uint8_t I1_CLICK
Enable CLICK interrupt on INT1.
uint8_t _RESERVED0
Reserved bit.
uint8_t I1_WTM
Enable FIFO watermark interrupt on INT1.
uint8_t I1_IA1
Enable IA1 interrupt on INT1.
uint8_t reg
Type used for register access.
uint8_t I1_ZYXDA
Enable ZYXDA interrupt on INT1.
CTRL_REG4 definitions.
uint8_t ST
Self-test enable.
uint8_t BDU
Block data update.
uint8_t BLE
Big/Little endian data selection.
uint8_t FS
Full-scale selection.
uint8_t reg
Type used for register access.
uint8_t SPIM
SPI serial interface mode selection (SIM)
uint8_t HR
Operating mode.
CTRL_REG5 definitions.
uint8_t D4D_INT2
4D detection enabled on INT2
uint8_t reg
Type used for register access.
uint8_t LIR_INT2
Latch interrupt request for INT2.
uint8_t D4D_INT1
4D detection enabled on INT1
uint8_t FIFO_EN
FIFO enable.
uint8_t _RESERVED
Reserved bits.
uint8_t LIR_INT1
Latch interrupt request for INT2.
uint8_t BOOT
Clears the data content.
CTRL_REG6 definitions.
uint8_t I2_IA1
Enable IA1 on INT2.
uint8_t I2_ACT
Enable activity interrupt on INT2.
uint8_t INT_POLARITY
Set pin polarity for INT1 and INT2.
uint8_t _RESERVED2
Reserved bit.
uint8_t _RESERVED0
Reserved bit.
uint8_t I2_IA2
Enable IA2 on INT2.
uint8_t reg
Type used for register access.
uint8_t I2_BOOT
Enable boot on INT2.
uint8_t I2_CLICK
Enable CLICK interrupt on INT2.
FIFO_CTRL_REG definitions.
uint8_t FTH
Set the watermark level for FIFO.
uint8_t TR
Triggering selection, FIFO event triggers INT1 or INT2.
uint8_t reg
Type used for register access.
uint8_t FM
FIFO mode selection.
FIFO_SRC_REG definitions.
uint8_t reg
Type used for register access.
uint8_t EMPTY
FIFO is empty.
uint8_t FSS
Number of unread samples in FIFO.
uint8_t WTM
FIFO content watermark level.
uint8_t OVRN_FIFO
Overrun in FIFO occurred.
INT1_CFG definitions.
uint8_t YLIE
Enable interrupt on Y low event.
uint8_t ZLIE
Enable interrupt on Z low event.
uint8_t AOI
AND/OR combination of interrupt events.
uint8_t ZHIE
Enable interrupt on Z high event.
uint8_t D6D
6 direction detection function enable
uint8_t reg
Type used for register access.
uint8_t YHIE
Enable interrupt on Y high event.
uint8_t XHIE
Enable interrupt on X high event.
uint8_t XLIE
Enable interrupt on X low event.
INT1_DURATION definitions.
uint8_t _RESERVED
need to be zero
uint8_t reg
Type used for register access.
uint8_t D
Sets the minimum duration of INT1, in ODR cycles.
INT1_THS definitions.
uint8_t reg
Type used for register access.
uint8_t THS
Sets threshold level, the LSB changes according to LIS2DH12_SCALE (@2G LSB=16mg; @4G LSB=32mg; @8G LS...
uint8_t _RESERVED
needs to be zero
INT2_CFG definitions.
uint8_t XLIE
Enable interrupt on X low event.
uint8_t reg
Type used for register access.
uint8_t YHIE
Enable interrupt on Y high event.
uint8_t YLIE
Enable interrupt on Y low event.
uint8_t AOI
AND/OR combination of interrupt events.
uint8_t ZLIE
Enable interrupt on Z low event.
uint8_t D6D
6 direction detection function enable
uint8_t XHIE
Enable interrupt on X high event.
uint8_t ZHIE
Enable interrupt on Z high event.
INT2_DURATION definitions.
uint8_t D
Sets the minimum duration of INT2, in ODR cycles.
uint8_t _RESERVED
need to be zero
uint8_t reg
Type used for register access.
INT2_THS definitions.
uint8_t reg
Type used for register access.
uint8_t _RESERVED
needs to be zero
uint8_t THS
Sets threshold level, LSB according to LIS2DH12_SCALE.
REFERENCE definitions.
uint8_t reg
Set reference value.
TEMP_CFG_REG definitions.
uint8_t _RESERVED
Should always be zero.
uint8_t TEMP_EN
"00" disables Temperature sensor, "11" enables
uint8_t reg
Type used for register access.
TIME_LATENCY definitions.
uint8_t reg
Sets time latency, in ODR cycles.
TIME_LIMIT definitions.
uint8_t reg
Type used for register access.
uint8_t _RESERVED
reserved bit
uint8_t TLI
Click time limit, in ODR cycles.
TIME_WINDOW definitions.
uint8_t reg
Sets time window, in ODR cycles.