Internal addresses, registers, constants for the Si1133 sensors family.
Internal addresses, registers, constants for the Si1133 sensor.
- Author
- iosabi iosab.nosp@m.i@pr.nosp@m.otonm.nosp@m.ail..nosp@m.com
Definition in file si1133_internals.h.
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- Note
- These parameters are not accessible directly from the I2C registers. Instead, to access these parameters SI1133_CMD_PARAM_QUERY and SI1133_CMD_PARAM_SET commands should be used.
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#define | SI1133_PARAM_I2C_ADDR (0x00) |
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#define | SI1133_PARAM_CHAN_LIST (0x01) |
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#define | SI1133_PARAM_ADCCONFIG0 (0x02) |
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#define | SI1133_PARAM_ADCSENS0 (0x03) |
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#define | SI1133_PARAM_ADCPOST0 (0x04) |
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#define | SI1133_PARAM_MEASCONFIG0 (0x05) |
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#define | SI1133_PARAM_ADCCONFIG1 (0x06) |
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#define | SI1133_PARAM_ADCSENS1 (0x07) |
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#define | SI1133_PARAM_ADCPOST1 (0x08) |
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#define | SI1133_PARAM_MEASCONFIG1 (0x09) |
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#define | SI1133_PARAM_ADCCONFIG2 (0x0a) |
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#define | SI1133_PARAM_ADCSENS2 (0x0b) |
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#define | SI1133_PARAM_ADCPOST2 (0x0c) |
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#define | SI1133_PARAM_MEASCONFIG2 (0x0d) |
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#define | SI1133_PARAM_ADCCONFIG3 (0x0e) |
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#define | SI1133_PARAM_ADCSENS3 (0x0f) |
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#define | SI1133_PARAM_ADCPOST3 (0x10) |
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#define | SI1133_PARAM_MEASCONFIG3 (0x11) |
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#define | SI1133_PARAM_ADCCONFIG4 (0x12) |
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#define | SI1133_PARAM_ADCSENS4 (0x13) |
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#define | SI1133_PARAM_ADCPOST4 (0x14) |
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#define | SI1133_PARAM_MEASCONFIG4 (0x15) |
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#define | SI1133_PARAM_ADCCONFIG5 (0x16) |
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#define | SI1133_PARAM_ADCSENS5 (0x17) |
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#define | SI1133_PARAM_ADCPOST5 (0x18) |
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#define | SI1133_PARAM_MEASCONFIG5 (0x19) |
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#define | SI1133_PARAM_MEASRATE_H (0x1a) |
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#define | SI1133_PARAM_MEASRATE_L (0x1b) |
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#define | SI1133_PARAM_MEASCOUNT0 (0x1c) |
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#define | SI1133_PARAM_MEASCOUNT1 (0x1d) |
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#define | SI1133_PARAM_MEASCOUNT2 (0x1e) |
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#define | SI1133_PARAM_THRESHOLD0_H (0x25) |
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#define | SI1133_PARAM_THRESHOLD0_L (0x26) |
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#define | SI1133_PARAM_THRESHOLD1_H (0x27) |
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#define | SI1133_PARAM_THRESHOLD1_L (0x28) |
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#define | SI1133_PARAM_THRESHOLD2_H (0x29) |
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#define | SI1133_PARAM_THRESHOLD2_L (0x2a) |
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#define | SI1133_PARAM_BURST (0x2b) |
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#define | SI1133_RESP0_COUNTER_MASK (0x0f) |
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#define | SI1133_RESP0_CMD_ERR_MASK (0x10) |
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#define | SI1133_RESP0_SLEEP_MASK (0x20) |
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#define | SI1133_RESP0_SUSPEND_MASK (0x40) |
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#define | SI1133_RESP0_RUNNING_MASK (0x80) |
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#define | SI1133_RESP0_ERR_INVALID_COMMAND (0x01) |
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#define | SI1133_RESP0_ERR_INVALID_PARAM_ADDR (0x80) |
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#define | SI1133_RESP0_ERR_ADC_OVERFLOW (0x88) |
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#define | SI1133_RESP0_ERR_BUFFER_OVERFLOW (0x89) |
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#define | SI1133_ADCCONFIG_DECIM_RATE_MASK (0x60) |
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#define | SI1133_ADCCONFIG_DECIM_RATE_SHIFT (5u) |
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#define | SI1133_ADCCONFIG_ADCMUX_MASK (0x1f) |
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#define | SI1133_ADCCONFIG_ADCMUX_SHIFT (0u) |
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#define | SI1133_ADCSENS_HSIG_MASK (0x80) |
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#define | SI1133_ADCSENS_SW_GAIN_MASK (0x70) |
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#define | SI1133_ADCSENS_SW_GAIN_SHIFT (4u) |
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#define | SI1133_ADCSENS_HW_GAIN_MASK (0x0f) |
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#define | SI1133_ADCSENS_HW_GAIN_SHIFT (0u) |
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#define | SI1133_ADCPOST_24BIT_OUT_MASK (0x40) |
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#define | SI1133_ADCPOST_POSTSHIFT_MASK (0x38) |
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#define | SI1133_ADCPOST_POSTSHIFT_SHIFT (3u) |
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#define | SI1133_ADCPOST_THRESH_SEL_MASK (0x03) |
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#define | SI1133_ADCPOST_THRESH_SEL_SHIFT (0u) |
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#define | SI1133_MEASCONFIG_COUNTER_IDX_MASK (0xc0) |
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#define | SI1133_MEASCONFIG_COUNTER_IDX_SHIFT (6u) |
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