clk_conf.h
1 /*
2  * Copyright (C) 2017 OTA keys S.A.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
17 #ifndef CLK_CONF_H
18 #define CLK_CONF_H
19 
20 #include <stdbool.h>
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
30 enum fam {
31  STM32F0,
32  STM32F1,
33  STM32F2,
34  STM32F3,
35  STM32F4,
36  STM32F7,
37  STM32MP1,
38  FAM_MAX,
39 };
46 enum {
47  STM32F030,
48  STM32F070,
49  STM32F031,
50  STM32F051,
51  STM32F071,
52  STM32F091,
53  STM32F042,
54  STM32F072,
55  STM32F038,
56  STM32F048,
57  STM32F058,
58  STM32F078,
59  STM32F098,
60 
61  STM32F100,
62  STM32F101,
63  STM32F102,
64  STM32F103,
65 
66  STM32F205,
67  STM32F207,
68  STM32F215,
69  STM32F217,
70 
71  STM32F301,
72  STM32F302,
73  STM32F303,
74  STM32F334,
75  STM32F373,
76  STM32F318,
77  STM32F328,
78  STM32F358,
79  STM32F378,
80  STM32F398,
81 
82  STM32F401,
83  STM32F405,
84  STM32F407,
85  STM32F410,
86  STM32F411,
87  STM32F412,
88  STM32F413,
89  STM32F415,
90  STM32F417,
91  STM32F423,
92  STM32F427,
93  STM32F429,
94  STM32F437,
95  STM32F439,
96  STM32F446,
97  STM32F469,
98  STM32F479,
99 
100  STM32F722,
101  STM32F732,
102  STM32F746,
103  STM32F756,
104  STM32F767,
105  STM32F769,
106  STM32F777,
107  STM32F779,
108 
109  MODEL_F_MAX,
110 };
111 
112 enum {
113  STM32MP157,
114 
115  MODEL_MP_MAX,
116 };
144 typedef struct {
145  unsigned min_vco_input;
146  unsigned max_vco_input;
147  unsigned min_vco_output;
148  unsigned max_vco_output;
150  unsigned min_n;
151  unsigned max_n;
152  unsigned inc_n;
154  unsigned min_m;
155  unsigned max_m;
156  unsigned inc_m;
158  unsigned min_p;
159  unsigned max_p;
160  unsigned inc_p;
162  unsigned min_q;
163  unsigned max_q;
164  unsigned inc_q;
165 } pll_cfg_t;
166 
170 typedef struct {
171  enum fam family;
173  unsigned max_coreclock;
174  unsigned max_apb1;
175  unsigned max_apb2;
176  unsigned max_apb3;
178  unsigned hsi;
180  pll_cfg_t pll;
182  bool has_pll_i2s;
183  bool has_pll_sai;
184  bool has_pll_i2s_m;
185  bool has_pll_sai_m;
186  bool has_pll_i2s_alt_input;
188  unsigned hsi_prediv;
190  int has_alt_48MHz;
191  bool need_48MHz;
192 } clk_cfg_t;
193 
198 #define ALT_48MHZ_NO 0
199 #define ALT_48MHZ_I2S 1
200 #define ALT_48MHZ_SAI 2
201 
202 #define ALT_48MHZ_Q 0
203 #define ALT_48MHZ_P 4
206 #define STM32F(x) [STM32F##x] = x
207 #define STM32F0(x) [STM32F0##x] = x
208 
210 static const unsigned stm32_f_model[] = {
211  STM32F0(30),
212  STM32F0(70),
213  STM32F0(31),
214  STM32F0(51),
215  STM32F0(71),
216  STM32F0(91),
217  STM32F0(42),
218  STM32F0(72),
219  STM32F0(38),
220  STM32F0(48),
221  STM32F0(58),
222  STM32F0(78),
223  STM32F0(98),
224 
225  STM32F(100),
226  STM32F(101),
227  STM32F(102),
228  STM32F(103),
229 
230  STM32F(205),
231  STM32F(207),
232  STM32F(215),
233  STM32F(217),
234 
235  STM32F(301),
236  STM32F(302),
237  STM32F(303),
238  STM32F(334),
239  STM32F(373),
240  STM32F(318),
241  STM32F(328),
242  STM32F(358),
243  STM32F(378),
244  STM32F(398),
245 
246  STM32F(401),
247  STM32F(405),
248  STM32F(407),
249  STM32F(410),
250  STM32F(411),
251  STM32F(412),
252  STM32F(413),
253  STM32F(415),
254  STM32F(417),
255  STM32F(423),
256  STM32F(427),
257  STM32F(429),
258  STM32F(437),
259  STM32F(439),
260  STM32F(446),
261  STM32F(469),
262  STM32F(479),
263 
264  STM32F(722),
265  STM32F(732),
266  STM32F(746),
267  STM32F(756),
268  STM32F(767),
269  STM32F(769),
270  STM32F(777),
271  STM32F(779),
272 };
273 
274 #define STM32MP(x) [STM32MP##x] = x
275 
277 static const unsigned stm32_model_mp[] = {
278  STM32MP(157),
279 };
280 
282 #define stm32f2_4_192_pll_cfg { \
283  .min_vco_input = 1000000U, \
284  .max_vco_input = 2000000U, \
285  .min_vco_output = 192000000U, \
286  .max_vco_output = 432000000U, \
287  .min_n = 50, \
288  .max_n = 432, \
289  .inc_n = 1, \
290  .min_m = 2, \
291  .max_m = 63, \
292  .inc_m = 1, \
293  .min_p = 2, \
294  .max_p = 8, \
295  .inc_p = 2, \
296  .min_q = 2, \
297  .max_q = 15, \
298  .inc_q = 1, \
299 }
300 
302 #define stm32f4_7_pll_cfg { \
303  .min_vco_input = 1000000U, \
304  .max_vco_input = 2000000U, \
305  .min_vco_output = 192000000U, \
306  .max_vco_output = 432000000U, \
307  .min_n = 50, \
308  .max_n = 432, \
309  .inc_n = 1, \
310  .min_m = 2, \
311  .max_m = 63, \
312  .inc_m = 1, \
313  .min_p = 2, \
314  .max_p = 8, \
315  .inc_p = 2, \
316  .min_q = 2, \
317  .max_q = 15, \
318  .inc_q = 1, \
319 }
320 
322 #define stm32mp1_pll_cfg { \
323  .min_vco_input = 4000000U, \
324  .max_vco_input = 16000000U, \
325  .min_vco_output = 400000000U, \
326  .max_vco_output = 800000000U, \
327  .min_n = 25, \
328  .max_n = 100, \
329  .inc_n = 1, \
330  .min_m = 2, \
331  .max_m = 63, \
332  .inc_m = 1, \
333  .min_p = 2, \
334  .max_p = 127, \
335  .inc_p = 1, \
336  .min_q = 2, \
337  .max_q = 127, \
338  .inc_q = 1, \
339 }
340 
344 static const clk_cfg_t stm32_f_clk_cfg[] = {
345  [STM32F030 ... STM32F098] = {
346  .family = STM32F0,
347  .max_coreclock = 48000000U,
348  .max_apb1 = 48000000U,
349  .max_apb2 = 0,
350  .hsi = 8000000U,
351  .pll = {
352  .min_vco_input = 1000000U,
353  .max_vco_input = 24000000U,
354  .min_vco_output = 16000000U,
355  .max_vco_output = 48000000U,
356  .min_m = 1,
357  .max_m = 16,
358  .inc_m = 1,
359  .min_n = 2,
360  .max_n = 16,
361  .inc_n = 1,
362  .min_p = 1,
363  .max_p = 1,
364  .inc_p = 1,
365  },
366  .has_pll_i2s = false,
367  .has_pll_sai = false,
368  .has_pll_i2s_alt_input = false,
369  .has_alt_48MHz = 0,
370  .hsi_prediv = 2,
371  .need_48MHz = false,
372  },
373  [STM32F100] = {
374  .family = STM32F1,
375  .max_coreclock = 24000000U,
376  .max_apb1 = 24000000U,
377  .max_apb2 = 24000000U,
378  .hsi = 8000000U,
379  .pll = {
380  .min_vco_input = 1000000U,
381  .max_vco_input = 24000000U,
382  .min_vco_output = 16000000U,
383  .max_vco_output = 24000000U,
384  .min_m = 1,
385  .max_m = 16,
386  .inc_m = 1,
387  .min_n = 2,
388  .max_n = 16,
389  .inc_n = 1,
390  .min_p = 1,
391  .max_p = 1,
392  .inc_p = 1,
393  },
394  .has_pll_i2s = false,
395  .has_pll_sai = false,
396  .has_pll_i2s_alt_input = false,
397  .has_alt_48MHz = 0,
398  .hsi_prediv = 2,
399  .need_48MHz = false,
400  },
401  [STM32F101 ... STM32F103] = {
402  .family = STM32F1,
403  .max_coreclock = 72000000U,
404  .max_apb1 = 36000000U,
405  .max_apb2 = 72000000U,
406  .hsi = 8000000U,
407  .pll = {
408  .min_vco_input = 1000000U,
409  .max_vco_input = 25000000U,
410  .min_vco_output = 1000000U,
411  .max_vco_output = 72000000U,
412  .min_m = 1,
413  .max_m = 16,
414  .inc_m = 1,
415  .min_n = 2,
416  .max_n = 16,
417  .inc_n = 1,
418  .min_p = 1,
419  .max_p = 1,
420  .inc_p = 1,
421  },
422  .has_pll_i2s = false,
423  .has_pll_sai = false,
424  .has_pll_i2s_alt_input = false,
425  .has_alt_48MHz = 0,
426  .hsi_prediv = 2,
427  .need_48MHz = false,
428  },
429  [STM32F205 ... STM32F217] = {
430  .family = STM32F2,
431  .max_coreclock = 120000000U,
432  .max_apb1 = 30000000U,
433  .max_apb2 = 60000000U,
434  .hsi = 16000000U,
435  .pll = stm32f2_4_192_pll_cfg,
436  .has_pll_i2s = true,
437  .has_pll_sai = false,
438  .has_pll_i2s_alt_input = false,
439  .has_alt_48MHz = 0,
440  .need_48MHz = true,
441  },
442  [STM32F301 ... STM32F398] = {
443  .family = STM32F3,
444  .max_coreclock = 72000000U,
445  .max_apb1 = 36000000U,
446  .max_apb2 = 72000000U,
447  .hsi = 8000000U,
448  .pll = {
449  .min_vco_input = 1000000U,
450  .max_vco_input = 25000000U,
451  .min_vco_output = 1000000U,
452  .max_vco_output = 72000000U,
453  .min_m = 1,
454  .max_m = 16,
455  .inc_m = 1,
456  .min_n = 2,
457  .max_n = 16,
458  .inc_n = 1,
459  .min_p = 1,
460  .max_p = 1,
461  .inc_p = 1,
462  },
463  .has_pll_i2s = false,
464  .has_pll_sai = false,
465  .has_pll_i2s_alt_input = false,
466  .has_alt_48MHz = 0,
467  .hsi_prediv = 2,
468  .need_48MHz = false,
469  },
470  [STM32F401] = {
471  .family = STM32F4,
472  .max_coreclock = 84000000U,
473  .max_apb1 = 42000000U,
474  .max_apb2 = 84000000U,
475  .hsi = 16000000U,
476  .pll = stm32f2_4_192_pll_cfg,
477  .has_pll_i2s = true,
478  .has_pll_sai = false,
479  .has_pll_i2s_m = false,
480  .has_pll_i2s_alt_input = false,
481  .has_alt_48MHz = 0,
482  .need_48MHz = true,
483  },
484  [STM32F405 ... STM32F407] = {
485  .family = STM32F4,
486  .max_coreclock = 168000000U,
487  .max_apb1 = 42000000U,
488  .max_apb2 = 84000000U,
489  .hsi = 16000000U,
490  .pll = stm32f4_7_pll_cfg,
491  .has_pll_i2s = true,
492  .has_pll_sai = false,
493  .has_pll_i2s_m = false,
494  .has_pll_i2s_alt_input = false,
495  .has_alt_48MHz = 0,
496  .need_48MHz = true,
497  },
498  [STM32F410] = {
499  .family = STM32F4,
500  .max_coreclock = 100000000U,
501  .max_apb1 = 50000000U,
502  .max_apb2 = 100000000U,
503  .hsi = 16000000U,
504  .pll = stm32f4_7_pll_cfg,
505  .has_pll_i2s = false,
506  .has_pll_sai = false,
507  .has_pll_i2s_m = false,
508  .has_pll_i2s_alt_input = false,
509  .has_alt_48MHz = 0,
510  .need_48MHz = true,
511  },
512  [STM32F411] = {
513  .family = STM32F4,
514  .max_coreclock = 100000000U,
515  .max_apb1 = 50000000U,
516  .max_apb2 = 100000000U,
517  .hsi = 16000000U,
518  .pll = stm32f4_7_pll_cfg,
519  .has_pll_i2s = true,
520  .has_pll_sai = false,
521  .has_pll_i2s_m = true,
522  .has_pll_i2s_alt_input = false,
523  .has_alt_48MHz = 0,
524  .need_48MHz = true,
525  },
526  [STM32F412 ... STM32F413] = {
527  .family = STM32F4,
528  .max_coreclock = 100000000U,
529  .max_apb1 = 50000000U,
530  .max_apb2 = 100000000U,
531  .hsi = 16000000U,
532  .pll = stm32f4_7_pll_cfg,
533  .has_pll_i2s = true,
534  .has_pll_sai = true,
535  .has_pll_i2s_m = true,
536  .has_pll_sai_m = false,
537  .has_pll_i2s_alt_input = true,
538  .has_alt_48MHz = ALT_48MHZ_I2S,
539  .need_48MHz = true,
540  },
541  [STM32F415 ... STM32F417] = {
542  .family = STM32F4,
543  .max_coreclock = 168000000U,
544  .max_apb1 = 42000000U,
545  .max_apb2 = 84000000U,
546  .hsi = 16000000U,
547  .pll = stm32f4_7_pll_cfg,
548  .has_pll_i2s = true,
549  .has_pll_sai = false,
550  .has_pll_i2s_m = false,
551  .has_pll_i2s_alt_input = false,
552  .has_alt_48MHz = 0,
553  .need_48MHz = true,
554  },
555  [STM32F423] = {
556  .family = STM32F4,
557  .max_coreclock = 100000000U,
558  .max_apb1 = 50000000U,
559  .max_apb2 = 100000000U,
560  .hsi = 16000000U,
561  .pll = stm32f4_7_pll_cfg,
562  .has_pll_i2s = true,
563  .has_pll_sai = true,
564  .has_pll_i2s_m = true,
565  .has_pll_sai_m = false,
566  .has_pll_i2s_alt_input = true,
567  .has_alt_48MHz = ALT_48MHZ_I2S,
568  .need_48MHz = true,
569  },
570  [STM32F427 ... STM32F439] = {
571  .family = STM32F4,
572  .max_coreclock = 180000000U,
573  .max_apb1 = 45000000U,
574  .max_apb2 = 90000000U,
575  .hsi = 16000000U,
576  .pll = stm32f4_7_pll_cfg,
577  .has_pll_i2s = true,
578  .has_pll_sai = true,
579  .has_pll_i2s_m = false,
580  .has_pll_sai_m = false,
581  .has_pll_i2s_alt_input = false,
582  .has_alt_48MHz = 0,
583  .need_48MHz = true,
584  },
585  [STM32F446] = {
586  .family = STM32F4,
587  .max_coreclock = 180000000U,
588  .max_apb1 = 45000000U,
589  .max_apb2 = 90000000U,
590  .hsi = 16000000U,
591  .pll = stm32f4_7_pll_cfg,
592  .has_pll_i2s = true,
593  .has_pll_sai = true,
594  .has_pll_i2s_m = true,
595  .has_pll_sai_m = true,
596  .has_pll_i2s_alt_input = false,
597  .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
598  .need_48MHz = true,
599  },
600  [STM32F469 ... STM32F479] = {
601  .family = STM32F4,
602  .max_coreclock = 180000000U,
603  .max_apb1 = 45000000U,
604  .max_apb2 = 90000000U,
605  .hsi = 16000000U,
606  .pll = stm32f4_7_pll_cfg,
607  .has_pll_i2s = true,
608  .has_pll_sai = true,
609  .has_pll_i2s_m = false,
610  .has_pll_sai_m = false,
611  .has_pll_i2s_alt_input = false,
612  .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
613  .need_48MHz = true,
614  },
615  [STM32F722 ... STM32F779] = {
616  .family = STM32F7,
617  .max_coreclock = 216000000U,
618  .max_apb1 = 54000000U,
619  .max_apb2 = 108000000U,
620  .hsi = 16000000U,
621  .pll = stm32f4_7_pll_cfg,
622  .has_pll_i2s = true,
623  .has_pll_sai = true,
624  .has_pll_i2s_m = false,
625  .has_pll_sai_m = false,
626  .has_pll_i2s_alt_input = false,
627  .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
628  .need_48MHz = true,
629  },
630 };
631 
635 static const clk_cfg_t stm32_mp_clk_cfg[] = {
636  [STM32MP157] = {
637  .family = STM32MP1,
638  .max_coreclock = 209000000U,
639  .max_apb1 = 104500000U,
640  .max_apb2 = 104500000U,
641  .max_apb3 = 104500000U,
642  .hsi = 64000000U,
643  .pll = stm32mp1_pll_cfg,
644  .has_pll_i2s = false,
645  .has_pll_sai = false,
646  .has_pll_i2s_m = false,
647  .has_pll_sai_m = false,
648  .has_pll_i2s_alt_input = false,
649  .has_alt_48MHz = 0,
650  .need_48MHz = true,
651  },
652 };
653 
654 #ifdef __cplusplus
655 }
656 #endif
657 
658 #endif /* CLK_CONF_H */
clk_cfg_t
Clock configuration.
Definition: clk_conf.h:170
clk_cfg_t::max_apb1
unsigned max_apb1
Max APB1 clock.
Definition: clk_conf.h:174
clk_cfg_t::has_pll_i2s_m
bool has_pll_i2s_m
PLL I2S has a M factor.
Definition: clk_conf.h:184
clk_cfg_t::max_coreclock
unsigned max_coreclock
Max coreclock.
Definition: clk_conf.h:173
clk_cfg_t::hsi
unsigned hsi
HSI frequency.
Definition: clk_conf.h:178
clk_cfg_t::has_pll_i2s
bool has_pll_i2s
PLL I2S available.
Definition: clk_conf.h:182
clk_cfg_t::family
enum fam family
Family.
Definition: clk_conf.h:171
clk_cfg_t::max_apb3
unsigned max_apb3
Max APB3 clock.
Definition: clk_conf.h:176
clk_cfg_t::pll
pll_cfg_t pll
PLL configuration.
Definition: clk_conf.h:180
clk_cfg_t::has_pll_sai
bool has_pll_sai
PLL SAI available.
Definition: clk_conf.h:183
clk_cfg_t::has_pll_i2s_alt_input
bool has_pll_i2s_alt_input
PLL I2S has an external input available.
Definition: clk_conf.h:186
clk_cfg_t::has_alt_48MHz
int has_alt_48MHz
48MHz can be generated by an alternate source
Definition: clk_conf.h:190
clk_cfg_t::hsi_prediv
unsigned hsi_prediv
Value if HSI has a fixed prediv, 0 otherwise.
Definition: clk_conf.h:188
clk_cfg_t::need_48MHz
bool need_48MHz
48MHz is needed
Definition: clk_conf.h:191
clk_cfg_t::max_apb2
unsigned max_apb2
Max APB2 clock.
Definition: clk_conf.h:175
clk_cfg_t::has_pll_sai_m
bool has_pll_sai_m
PLL SAI has a M factor.
Definition: clk_conf.h:185
pll_cfg_t
PLL configuration parameters.
Definition: clk_conf.h:144
pll_cfg_t::min_vco_output
unsigned min_vco_output
Min VCO output.
Definition: clk_conf.h:147
pll_cfg_t::max_n
unsigned max_n
Max N.
Definition: clk_conf.h:151
pll_cfg_t::max_vco_input
unsigned max_vco_input
Max VCO input.
Definition: clk_conf.h:146
pll_cfg_t::min_vco_input
unsigned min_vco_input
Min VCO input.
Definition: clk_conf.h:145
pll_cfg_t::min_m
unsigned min_m
Min M.
Definition: clk_conf.h:154
pll_cfg_t::max_m
unsigned max_m
Max M.
Definition: clk_conf.h:155
pll_cfg_t::min_n
unsigned min_n
Min N.
Definition: clk_conf.h:150
pll_cfg_t::max_p
unsigned max_p
Max P.
Definition: clk_conf.h:159
pll_cfg_t::inc_n
unsigned inc_n
Increment between two values of N.
Definition: clk_conf.h:152
pll_cfg_t::inc_m
unsigned inc_m
Increment between two values of M.
Definition: clk_conf.h:156
pll_cfg_t::min_p
unsigned min_p
Min P.
Definition: clk_conf.h:158
pll_cfg_t::inc_p
unsigned inc_p
Increment between two values of P.
Definition: clk_conf.h:160
pll_cfg_t::min_q
unsigned min_q
Min Q.
Definition: clk_conf.h:162
pll_cfg_t::max_q
unsigned max_q
Max Q.
Definition: clk_conf.h:163
pll_cfg_t::max_vco_output
unsigned max_vco_output
Max VCO output.
Definition: clk_conf.h:148