cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universität Berlin
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_COMMON_H
22 #define PERIPH_CPU_COMMON_H
23 
24 #include <stdint.h>
25 
26 #include "cpu_conf.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 #ifdef Doxygen
37 #define STM32_BOOTLOADER_ADDR
38 #endif
39 
45 #define CPUID_LEN (12U)
46 
50 #ifndef CPUID_ADDR
51 #define CPUID_ADDR (UID_BASE)
52 #endif
53 
57 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
58  defined(CPU_FAM_STM32F3)
59 #define CLOCK_LSI (40000U)
60 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
61 #define CLOCK_LSI (37000U)
62 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
63  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
64  defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
65  defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
66  defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
67  defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
68 #define CLOCK_LSI (32000U)
69 #else
70 #error "error: LSI clock speed not defined for your target CPU"
71 #endif
72 
73 /* if CPU has APB1 bus */
74 #if defined(CPU_FAM_STM32G4) || \
75  defined(CPU_FAM_STM32L4) || \
76  defined(CPU_FAM_STM32L5) || \
77  defined(CPU_FAM_STM32U5) || \
78  defined(CPU_FAM_STM32WB) || \
79  defined(CPU_FAM_STM32WL)
80  #define APB1_PERIPH_EN RCC->APB1ENR1
81  #define APB12_PERIPH_EN RCC->APB1ENR2
82 #elif defined(CPU_FAM_STM32C0) || \
83  defined(CPU_FAM_STM32G0)
84  #define APB1_PERIPH_EN RCC->APBENR1
85  #define APB12_PERIPH_EN RCC->APBENR2
86 #elif defined(CPU_FAM_STM32MP1)
87  #define APB1_PERIPH_EN RCC->MC_APB1ENSETR
88  #define APB1_PERIPH_DIS RCC->MC_APB1ENCLRR
89 #elif defined(APB1PERIPH_BASE) || \
90  defined(CPU_FAM_STM32F0) || \
91  defined(CPU_FAM_STM32L0)
92  #define APB1_PERIPH_EN RCC->APB1ENR
93 #endif
94 
95 /* if CPU has APB2 bus */
96 #if defined(CPU_FAM_STM32MP1)
97  #define APB2_PERIPH_EN RCC->MC_APB2ENSETR
98  #define APB2_PERIPH_DIS RCC->MC_APB2ENCLRR
99 #elif defined(APB2PERIPH_BASE) || \
100  defined(CPU_FAM_STM32F0) || \
101  defined(CPU_FAM_STM32L0)
102  #define APB2_PERIPH_EN RCC->APB2ENR
103 #endif
104 
105 /* if CPU has APB3 bus */
106 #if defined(CPU_FAM_STM32WB)
107  /* CPU has APB3, but no periph enable registers for the bus. */
108  #undef APB3_PERIPH_EN /* not defined */
109 #elif defined(APB3PERIPH_BASE) || \
110  defined(APB3PERIPH_BASE_S)
111  #define APB3_PERIPH_EN RCC->APB3ENR
112 #endif
113 
114 /* if CPU has AHB/AHB1 bus */
115 #if defined(AHBPERIPH_BASE) || \
116  defined(CPU_FAM_STM32F3)
117  #define AHB_PERIPH_EN RCC->AHBENR
118 #elif defined(CPU_FAM_STM32MP1)
119  /* CPU has AHB1, but no periph enable registers for the bus. */
120  #undef AHB1_PERIPH_EN /* not defined */
121  #undef AHB1_PERIPH_DIS /* not defined */
122 #elif defined(AHB1PERIPH_BASE)
123  #define AHB1_PERIPH_EN RCC->AHB1ENR
124 #endif
125 
126 /* if CPU has AHB2 bus */
127 #if defined(CPU_FAM_STM32F0) || \
128  defined(CPU_FAM_STM32F3)
129  /* CPU has AHB2, but no periph enable registers for the bus. */
130  #undef AHB2_PERIPH_EN /* not defined */
131 #elif defined(CPU_FAM_STM32U5)
132  #define AHB2_PERIPH_EN RCC->AHB2ENR1
133  #define AHB22_PERIPH_EN RCC->AHB2ENR2
134 #elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB2_SUPPORT)
135  #define AHB2_PERIPH_EN RCC->AHB2ENR
136 #elif defined(CPU_FAM_STM32MP1)
137  #define AHB2_PERIPH_EN RCC->MC_AHB2ENSETR
138  #define AHB2_PERIPH_DIS RCC->MC_AHB2ENCLRR
139 #elif defined(AHB2PERIPH_BASE)
140  #define AHB2_PERIPH_EN RCC->AHB2ENR
141 #endif
142 
143 /* if CPU has AHB3 bus */
144 #if defined(CPU_FAM_STM32F3)
145  /* CPU has AHB3, but no periph enable registers for the bus. */
146  #undef AHB3_PERIPH_EN /* not defined */
147 #elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB3_SUPPORT)
148  #define AHB3_PERIPH_EN RCC->AHB3ENR
149 #elif defined(CPU_FAM_STM32MP1)
150  #define AHB3_PERIPH_EN RCC->MC_AHB3ENSETR
151  #define AHB3_PERIPH_DIS RCC->MC_AHB3ENCLRR
152 #elif defined(AHB3PERIPH_BASE) || \
153  defined(AHB3PERIPH_BASE_S) || \
154  defined(CPU_FAM_STM32F2) || \
155  defined(CPU_FAM_STM32F7) || \
156  defined(CPU_FAM_STM32G4) || \
157  defined(CPU_FAM_STM32L4)
158  #define AHB3_PERIPH_EN RCC->AHB3ENR
159 #endif
160 
161 /* if CPU has AHB4 bus */
162 #if defined(CPU_FAM_STM32MP1)
163  #define AHB4_PERIPH_EN RCC->MC_AHB4ENSETR
164  #define AHB4_PERIPH_DIS RCC->MC_AHB4ENCLRR
165 #elif defined(AHB4PERIPH_BASE)
166  /* AHB3ENR is not a typo here. It controls both AHB3 and AHB4. */
167  #define AHB4_PERIPH_EN RCC->AHB3ENR
168 #endif
169 
170 /* if CPU has IOP bus */
171 #if defined(IOPPERIPH_BASE) || \
172  defined(RCC_IOPENR_GPIOAEN) || \
173  defined(RCC_IOPENR_IOPAEN)
174  #define IOP_PERIPH_EN RCC->IOPENR
175 #endif
176 
180 typedef enum {
181 #if defined(APB1_PERIPH_EN)
182  APB1,
183 #endif
184 #if defined(APB12_PERIPH_EN)
185  APB12,
186 #endif
187 #if defined(APB2_PERIPH_EN)
188  APB2,
189 #endif
190 #if defined(APB3_PERIPH_EN)
191  APB3,
192 #endif
193 #if defined(AHB_PERIPH_EN)
194  AHB,
195 #endif
196 #if defined(AHB1_PERIPH_EN)
197  AHB1,
198 #endif
199 #if defined(AHB2_PERIPH_EN)
200  AHB2,
201 #endif
202 #if defined(AHB22_PERIPH_EN)
203  AHB22,
204 #endif
205 #if defined(AHB3_PERIPH_EN)
206  AHB3,
207 #endif
208 #if defined(AHB4_PERIPH_EN)
209  AHB4,
210 #endif
211 #if defined(IOP_PERIPH_EN)
212  IOP,
213 #endif
214  BUS_NUMOF
215 } bus_t;
216 
224 uint32_t periph_apb_clk(bus_t bus);
225 
233 uint32_t periph_timer_clk(bus_t bus);
234 
241 void periph_clk_en(bus_t bus, uint32_t mask);
242 
249 void periph_clk_dis(bus_t bus, uint32_t mask);
250 
257 void periph_lpclk_en(bus_t bus, uint32_t mask);
258 
265 void periph_lpclk_dis(bus_t bus, uint32_t mask);
266 
267 #ifdef __cplusplus
268 }
269 #endif
270 
271 #endif /* PERIPH_CPU_COMMON_H */
bus_t
bus_t
On-Chip buses.
Definition: periph_cpu.h:77
APB1
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
AHB
@ AHB
Advanced High-performance Bus.
Definition: periph_cpu.h:78
APB2
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:80
periph_apb_clk
uint32_t periph_apb_clk(bus_t bus)
Get the actual bus clock frequency for the APB buses.
periph_lpclk_en
void periph_lpclk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock in low power mode.
periph_clk_en
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
periph_clk_dis
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.
periph_timer_clk
uint32_t periph_timer_clk(bus_t bus)
Get the actual timer clock frequency.
periph_lpclk_dis
void periph_lpclk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock in low power mode.
bus_t
bus_t
CPU specific LSI clock speed.
Definition: cpu_common.h:180
BUS_NUMOF
@ BUS_NUMOF
number of buses
Definition: cpu_common.h:214