Memory layout of GPIO control register in pads bank 0. More...

Detailed Description

Memory layout of GPIO control register in pads bank 0.

Definition at line 290 of file periph_cpu.h.

#include <periph_cpu.h>

Data Fields
uint32_t	slew_rate_fast: 1
	set slew rate control to fast

uint32_t	schmitt_trig_enable: 1
	enable Schmitt trigger

uint32_t	pull_down_enable: 1
	enable pull down resistor

uint32_t	pull_up_enable: 1
	enable pull up resistor

uint32_t	drive_strength: 2
	GPIO driver strength.

uint32_t	input_enable: 1
	enable as input

uint32_t	output_disable: 1
	disable output, overwrite output enable from peripherals

uint32_t	__pad0__: 24
	24 bits reserved for future use

The documentation for this struct was generated from the following file:

Data Fields