candev_stm32.h

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/*
 * SPDX-FileCopyrightText: 2016 OTA keys S.A.
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include "can/candev.h"
 
#if defined(CAN3)
#define CANDEV_STM32_CHAN_NUMOF 3
#elif defined(CAN2)
#define CANDEV_STM32_CHAN_NUMOF 2
#elif defined(CAN1) || defined(CAN) || DOXYGEN
#define CANDEV_STM32_CHAN_NUMOF 1
#else
#error "CAN STM32: CPU not supported"
#endif
 
#if defined(CPU_FAM_STM32F1)
#define ISR_CAN1_TX     isr_usb_hp_can1_tx
#define ISR_CAN1_RX0    isr_usb_lp_can1_rx0
#define ISR_CAN1_RX1    isr_can1_rx1
#define ISR_CAN1_SCE    isr_can1_sce
#else
#define ISR_CAN1_TX     isr_can1_tx
#define ISR_CAN1_RX0    isr_can1_rx0
#define ISR_CAN1_RX1    isr_can1_rx1
#define ISR_CAN1_SCE    isr_can1_sce
#define ISR_CAN2_TX     isr_can2_tx
#define ISR_CAN2_RX0    isr_can2_rx0
#define ISR_CAN2_RX1    isr_can2_rx1
#define ISR_CAN2_SCE    isr_can2_sce
#define ISR_CAN3_TX     isr_can3_tx
#define ISR_CAN3_RX0    isr_can3_rx0
#define ISR_CAN3_RX1    isr_can3_rx1
#define ISR_CAN3_SCE    isr_can3_sce
#endif
#if CANDEV_STM32_CHAN_NUMOF > 1 || DOXYGEN
#define CAN_STM32_NB_FILTER     28
#else
#define CAN_STM32_NB_FILTER     14
#endif
 
#ifndef CANDEV_STM32_DEFAULT_BITRATE
#define CANDEV_STM32_DEFAULT_BITRATE 500000U
#endif
 
#ifndef CANDEV_STM32_DEFAULT_SPT
#define CANDEV_STM32_DEFAULT_SPT     875
#endif
 
typedef struct {
    CAN_TypeDef *can;           
    uint32_t rcc_mask;          
    gpio_t rx_pin;              
    gpio_t tx_pin;              
#ifndef CPU_FAM_STM32F1
    gpio_af_t af;               
#endif
    bool en_deep_sleep_wake_up; 
#if CANDEV_STM32_CHAN_NUMOF > 1 || defined(DOXYGEN)
    CAN_TypeDef *can_master;    
    uint32_t master_rcc_mask;   
    uint8_t first_filter;
    uint8_t nb_filters;
#endif
#if defined(CPU_FAM_STM32F0)
    uint8_t irqn;                       
#else
    uint8_t tx_irqn;                    
    uint8_t rx0_irqn;                   
    uint8_t rx1_irqn;                   
    uint8_t sce_irqn;                   
#endif
    uint8_t ttcm : 1;                   
    uint8_t abom : 1;                   
    uint8_t awum : 1;                   
    uint8_t nart : 1;                   
    uint8_t rflm : 1;                   
    uint8_t txfp : 1;                   
    uint8_t lbkm : 1;                   
    uint8_t silm : 1;                   
} can_conf_t;
#define HAVE_CAN_CONF_T
 
#define CAN_STM32_TX_MAILBOXES 3
#define CAN_STM32_RX_MAILBOXES 2
 
#ifndef CAN_STM32_RX_MAIL_FIFO
#define CAN_STM32_RX_MAIL_FIFO 12
#endif
 
typedef struct can can_t;
#define HAVE_CAN_T
 
typedef struct candev_stm32_rx_fifo {
    struct can_frame frame[CAN_STM32_RX_MAIL_FIFO]; 
    int write_idx;                                  
    int read_idx;                                   
    int is_full;                                    
} candev_stm32_rx_fifo_t;
 
typedef struct candev_stm32_isr {
    int isr_tx : 3;     
    int isr_rx : 2;     
    int isr_wkup : 1;   
} candev_stm32_isr_t;
 
struct can {
    candev_t candev;                    
    const can_conf_t *conf;    
    gpio_t rx_pin;                      
    gpio_t tx_pin;                      
    gpio_af_t af;                       
    const struct can_frame *tx_mailbox[CAN_STM32_TX_MAILBOXES];
    candev_stm32_rx_fifo_t rx_fifo;     
    candev_stm32_isr_t isr_flags;       
};
 
#ifndef CPU_FAM_STM32F1
void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin,
                           gpio_af_t af);
#else
void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin);
#endif
 
#ifdef __cplusplus
}
#endif