cpu_dma.h
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1 /*
2  * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
3  * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4  * SPDX-License-Identifier: LGPL-2.1-only
5  */
6 
7 #pragma once
8 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
28 typedef struct {
51  int stream;
52 } dma_conf_t;
53 
57 typedef unsigned dma_t;
58 
62 typedef enum {
66 } dma_mode_t;
67 
71 typedef enum {
76 } dma_burst_t;
77 
81 typedef enum {
87 
92 #define DMA_CHAN_CONFIG_UNSUPPORTED (UINT8_MAX)
93 
98 #define DMA_INC_SRC_ADDR (0x04)
99 #define DMA_INC_DST_ADDR (0x08)
100 #define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)
107 #define DMA_DATA_WIDTH_BYTE (0x00)
108 #define DMA_DATA_WIDTH_HALF_WORD (0x01)
109 #define DMA_DATA_WIDTH_WORD (0x02)
112 #ifdef MODULE_PERIPH_DMA
116 #define DMA_STREAM_UNDEF (UINT_MAX)
117 
121 void dma_init(void);
122 
139 int dma_transfer(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
140  dma_mode_t mode, uint8_t flags);
141 
147 void dma_acquire(dma_t dma);
148 
154 void dma_release(dma_t dma);
155 
164 void dma_start(dma_t dma);
165 
173 uint16_t dma_suspend(dma_t dma);
174 
181 void dma_resume(dma_t dma, uint16_t remaining);
182 
188 void dma_stop(dma_t dma);
189 
195 void dma_wait(dma_t dma);
196 
210 int dma_configure(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
211  dma_mode_t mode, uint8_t flags);
212 
227 void dma_setup(dma_t dma, int chan, void *periph_addr, dma_mode_t mode,
228  uint8_t width, bool inc_periph);
229 
250 void dma_setup_ext(dma_t dma, dma_burst_t pburst, dma_burst_t mburst,
251  bool fifo, dma_fifo_thresh_t thresh, bool pfctrl);
252 
261 void dma_prepare(dma_t dma, void *mem, size_t len, bool incr_mem);
262 
263 #endif /* MODULE_PERIPH_DMA */
264 
265 #ifdef __cplusplus
266 }
267 #endif
268 
dma_burst_t
Burst Transfer modes for F2/F4/F7.
Definition: cpu_dma.h:71
@ DMA_BURST_INCR4
incremental burst of 4 beats
Definition: cpu_dma.h:73
@ DMA_BURST_INCR8
incremental burst of 8 beats
Definition: cpu_dma.h:74
@ DMA_BURST_SINGLE
single transfer
Definition: cpu_dma.h:72
@ DMA_BURST_INCR16
incremental burst of 16 beats
Definition: cpu_dma.h:75
dma_fifo_thresh_t
Threshold selection in FIFO mode for F2/F4F7.
Definition: cpu_dma.h:81
@ DMA_FIFO_FULL_3_4
3/4 full FIFO
Definition: cpu_dma.h:84
@ DMA_FIFO_FULL_1_4
1/4 full FIFO
Definition: cpu_dma.h:82
@ DMA_FIFO_FULL_1_2
1/2 full FIFO
Definition: cpu_dma.h:83
@ DMA_FIFO_FULL
Full FIFO.
Definition: cpu_dma.h:85
unsigned dma_t
DMA type.
Definition: cpu_dma.h:57
dma_mode_t
DMA modes.
Definition: cpu_dma.h:62
@ DMA_PERIPH_TO_MEM
Peripheral to memory.
Definition: cpu_dma.h:63
@ DMA_MEM_TO_PERIPH
Memory to peripheral.
Definition: cpu_dma.h:64
@ DMA_MEM_TO_MEM
Memory to memory.
Definition: cpu_dma.h:65
void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst, size_t num, dma_incr_t incr)
Prepare the DMA channel for an individual transfer.
void dma_init(void)
Initialize DMA.
void dma_wait(dma_t dma)
Wait for a DMA channel to finish the transfer.
void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq)
Initialize a previously allocated DMA channel with one-time settings.
unsigned dma_t
DMA channel type.
void dma_start(dma_t dma)
Start a DMA transfer.
DMA configuration.
Definition: cpu_dma.h:28
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:51