cpu_qdec.h
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1 /*
2  * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
3  * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4  * SPDX-License-Identifier: LGPL-2.1-only
5  */
6 
7 #pragma once
8 
20 #include <stdint.h>
21 
22 #include "cpu.h"
23 #include "periph/cpu_gpio.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
32 #define QDEC_CHAN (2U)
33 
37 typedef struct {
38  gpio_t pin;
39  uint8_t cc_chan;
40 } qdec_chan_t;
41 
45 typedef struct {
46  TIM_TypeDef *dev;
47  uint32_t max;
48  uint32_t rcc_mask;
51 #ifdef CPU_FAM_STM32F1
52  uint32_t remap;
54 #else
56 #endif
57  uint8_t bus;
58  uint8_t irqn;
59 } qdec_conf_t;
60 
61 #ifdef __cplusplus
62 }
63 #endif
64 
GPIO CPU definitions for the STM32 family.
#define QDEC_CHAN
All STM QDEC timers have 2 capture channels.
Definition: cpu_qdec.h:32
gpio_af_t
Override alternative GPIO mode options.
Definition: periph_cpu.h:162
QDEC channel.
Definition: cpu_qdec.h:37
uint8_t cc_chan
capture compare channel used
Definition: cpu_qdec.h:39
gpio_t pin
GPIO pin mapped to this channel.
Definition: cpu_qdec.h:38
Quadrature decoder configuration struct.
uint32_t max
Maximum counter value.
Definition: cpu_qdec.h:47
uint8_t irqn
global IRQ channel
Definition: cpu_qdec.h:58
gpio_af_t af
alternate function used
Definition: cpu_qdec.h:55
uint32_t rcc_mask
bit in clock enable register
Definition: cpu_qdec.h:48
TIM_TypeDef * dev
Timer used.
Definition: cpu_qdec.h:46
uint8_t bus
APB bus.
Definition: cpu_qdec.h:57