periph_cpu.h
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1 /*
2  * SPDX-FileCopyrightText: 2015 Freie Universität Berlin
3  * SPDX-FileCopyrightText: 2015 Hamburg University of Applied Sciences
4  * SPDX-License-Identifier: LGPL-2.1-only
5  */
6 
7 #pragma once
8 
21 #include "periph_cpu_common.h"
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
31 #define PERIPH_SPI_NEEDS_INIT_CS
32 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
33 #define PERIPH_SPI_NEEDS_TRANSFER_REG
34 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
40 #define CPUID_LEN (16U)
41 
46 #define RTT_MAX_VALUE (0xffffffff)
47 #define RTT_CLOCK_FREQUENCY (CHIP_FREQ_XTAL_32K) /* in Hz */
48 #define RTT_MIN_FREQUENCY (1) /* in Hz */
49 #define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */
59 #define ADC_NUMOF (16U)
60 
72 #define DAC_NUMOF (2U)
73 
74 #ifndef DOXYGEN
79 #define HAVE_SPI_MODE_T
80 typedef enum {
81  SPI_MODE_0 = (SPI_CSR_NCPHA),
82  SPI_MODE_1 = (0),
83  SPI_MODE_2 = (SPI_CSR_CPOL | SPI_CSR_NCPHA),
84  SPI_MODE_3 = (SPI_CSR_CPOL)
85 } spi_mode_t;
92 #define HAVE_SPI_CLK_T
93 typedef enum {
94  SPI_CLK_100KHZ = (100000),
95  SPI_CLK_400KHZ = (400000),
96  SPI_CLK_1MHZ = (1000000),
97  SPI_CLK_5MHZ = (5000000),
98  SPI_CLK_10MHZ = (10000000)
99 } spi_clk_t;
101 #endif /* ndef DOXYGEN */
102 
103 #ifndef DOXYGEN
108 #define HAVE_ADC_RES_T
109 typedef enum {
110  ADC_RES_6BIT = 0x1,
111  ADC_RES_8BIT = 0x2,
112  ADC_RES_10BIT = ADC_MR_LOWRES_BITS_10,
113  ADC_RES_12BIT = ADC_MR_LOWRES_BITS_12,
114  ADC_RES_14BIT = 0x4,
115  ADC_RES_16BIT = 0x8
116 } adc_res_t;
118 #endif /* ndef DOXYGEN */
119 
123 typedef struct {
124  gpio_t pin;
125  uint8_t hwchan;
127 
131 typedef struct {
132  Spi *dev;
133  uint8_t id;
134  gpio_t clk;
135  gpio_t mosi;
136  gpio_t miso;
138 } spi_conf_t;
139 
140 #ifdef __cplusplus
141 }
142 #endif
143 
spi_clk_t
Definition: periph_cpu.h:348
adc_res_t
Possible ADC resolution settings.
Definition: adc.h:92
@ ADC_RES_16BIT
ADC resolution: 16 bit.
Definition: adc.h:98
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition: adc.h:94
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition: adc.h:97
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition: adc.h:93
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition: adc.h:95
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition: adc.h:96
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition: periph_cpu.h:40
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition: periph_cpu.h:42
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition: periph_cpu.h:41
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition: periph_cpu.h:43
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition: periph_cpu.h:353
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition: periph_cpu.h:352
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition: periph_cpu.h:350
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition: periph_cpu.h:351
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition: periph_cpu.h:349
spi_mode_t
Support SPI modes.
Definition: periph_cpu.h:39
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
PWM channel configuration.
Definition: periph_cpu.h:464
uint8_t hwchan
the HW channel used for a logical channel
Definition: periph_cpu.h:125
SPI device configuration.
Definition: periph_cpu.h:333
gpio_mux_t mux
pin MUX setting
Definition: periph_cpu.h:137
uint8_t id
corresponding ID of that module
Definition: periph_cpu.h:133
Spi * dev
SPI module to use.
Definition: periph_cpu.h:132
gpio_t clk
pin mapped to the CLK line
Definition: periph_cpu.h:134