periph_cpu_common.h
Go to the documentation of this file.
1 /*
2  * SPDX-FileCopyrightText: 2025 Mesotic SAS
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
19 #include "cpu.h"
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
25 #ifndef DOXYGEN
26 #define HAVE_GPIO_T
27 typedef uint32_t gpio_t;
28 
29 #define GPIO_UNDEF (0xffffffff)
30 
31 #define GPIO_PIN(x, y) (((uint32_t)PIOA + (x << 9)) | y)
32 #endif /* DOXYGEN */
33 
42 #define TIMER_CHANNEL_NUMOF (1)
43 
52 #define GPIO_MODE(io, pu, od) (io | (pu << 1) | (od << 2))
53 
54 #ifndef DOXYGEN
55 #define HAVE_GPIO_MODE_T
56 typedef enum {
57  GPIO_IN = GPIO_MODE(0, 0, 0),
58  GPIO_IN_PD = 0xf,
59  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
60  GPIO_OUT = GPIO_MODE(1, 0, 0),
61  GPIO_OD = GPIO_MODE(1, 0, 1),
62  GPIO_OD_PU = GPIO_MODE(1, 1, 1),
63 } gpio_mode_t;
64 
65 #define HAVE_GPIO_FLANK_T
66 typedef enum {
67  GPIO_RISING = 1,
68  GPIO_FALLING = 2,
69  GPIO_BOTH = 3
70 } gpio_flank_t;
71 #endif /* ndef DOXYGEN */
72 
76 typedef enum {
77  GPIO_MUX_A = 0,
78  GPIO_MUX_B = 1,
79 #ifdef CPU_FAM_SAM4S
80  GPIO_MUX_C = 2,
81  GPIO_MUX_D = 3,
82 #endif
83 } gpio_mux_t;
84 
88 enum {
89  PA = 0,
90  PB = 1,
91  PC = 2,
92 #ifdef CPU_FAM_SAM3
93  PD = 3,
94 #endif
95 };
96 
103 void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
104 
108 typedef struct {
109  Tc *dev;
110  uint8_t id_ch0;
111 } timer_conf_t;
112 
116 typedef struct {
117  Uart *dev;
118  gpio_t rx_pin;
119  gpio_t tx_pin;
120  gpio_mux_t mux;
121  uint8_t pmc_id;
122  uint8_t irqn;
123 } uart_conf_t;
124 
125 #ifdef __cplusplus
126 }
127 #endif
128 
@ GPIO_OUT
select GPIO MASK as output
Definition: periph_cpu.h:161
@ GPIO_IN
select GPIO MASK as input
Definition: periph_cpu.h:160
gpio_mode_t
Available pin modes.
Definition: periph_cpu.h:88
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:91
@ GPIO_FALLING
emit interrupt on falling flank
@ GPIO_RISING
emit interrupt on rising flank
@ GPIO_BOTH
not supported -> random value
@ GPIO_OD
configure as output in open-drain mode without pull resistor
Definition: gpio.h:123
@ GPIO_IN_PU
configure as input with pull-up resistor
Definition: gpio.h:121
@ GPIO_OD_PU
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:125
@ GPIO_IN_PD
configure as input with pull-down resistor
Definition: gpio.h:120
gpio_flank_t
Enumeration of supported GPIO flanks.
@ PB
port B
@ PC
port C
@ PA
port A
@ PD
port D
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Set up alternate function (PMUX setting) for a PORT pin.
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ GPIO_MUX_A
select peripheral function A
@ GPIO_MUX_B
select peripheral function B
#define GPIO_MODE(io, pu, od)
Generate GPIO mode bitfields.
Timer device configuration.
Definition: periph_cpu.h:260
Tc * dev
timer device
uint8_t id_ch0
ID of the timer's first channel.
UART device configuration.
Definition: periph_cpu.h:214
uint8_t pmc_id
bit in the PMC register of the device
Uart * dev
U(S)ART device used.