periph_cpu.h

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/*
 * SPDX-FileCopyrightText: 2018 Mesotic SAS
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once
 
#include "periph_cpu_common.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define PM_NUM_MODES        (2)
enum {
    SAM0_GCLK_MAIN = 0,                 
    SAM0_GCLK_32KHZ,                    
};
static const gpio_t sam0_adc_pins[1][10] = {
    {
        GPIO_PIN(PA, 2), GPIO_PIN(PA, 3), GPIO_PIN(PA, 4), GPIO_PIN(PA, 5),
        GPIO_PIN(PA, 6), GPIO_PIN(PA, 7), GPIO_PIN(PA, 8), GPIO_PIN(PA, 9),
        GPIO_PIN(PA, 10), GPIO_PIN(PA, 11)
    }
};
 
#define ADC_INPUTCTRL_MUXPOS_PA02 ADC_INPUTCTRL_MUXPOS_AIN0 
#define ADC_INPUTCTRL_MUXPOS_PA03 ADC_INPUTCTRL_MUXPOS_AIN1 
#define ADC_INPUTCTRL_MUXPOS_PA04 ADC_INPUTCTRL_MUXPOS_AIN2 
#define ADC_INPUTCTRL_MUXPOS_PA05 ADC_INPUTCTRL_MUXPOS_AIN3 
#define ADC_INPUTCTRL_MUXPOS_PA06 ADC_INPUTCTRL_MUXPOS_AIN4 
#define ADC_INPUTCTRL_MUXPOS_PA07 ADC_INPUTCTRL_MUXPOS_AIN5 
#define ADC_INPUTCTRL_MUXPOS_PA08 ADC_INPUTCTRL_MUXPOS_AIN6 
#define ADC_INPUTCTRL_MUXPOS_PA09 ADC_INPUTCTRL_MUXPOS_AIN7 
#define ADC_INPUTCTRL_MUXPOS_PA10 ADC_INPUTCTRL_MUXPOS_AIN8 
#define ADC_INPUTCTRL_MUXPOS_PA11 ADC_INPUTCTRL_MUXPOS_AIN9 
#define ADC_INPUTCTRL_MUXNEG_PA02 ADC_INPUTCTRL_MUXPOS_AIN0 
#define ADC_INPUTCTRL_MUXNEG_PA03 ADC_INPUTCTRL_MUXPOS_AIN1 
#define ADC_INPUTCTRL_MUXNEG_PA04 ADC_INPUTCTRL_MUXPOS_AIN2 
#define ADC_INPUTCTRL_MUXNEG_PA05 ADC_INPUTCTRL_MUXPOS_AIN3 
#define ADC_INPUTCTRL_MUXNEG_PA06 ADC_INPUTCTRL_MUXPOS_AIN4 
#define ADC_INPUTCTRL_MUXNEG_PA07 ADC_INPUTCTRL_MUXPOS_AIN5 
#define ADC_INPUTCTRL_MUXNEG_PA08 ADC_INPUTCTRL_MUXPOS_AIN6 
#define ADC_INPUTCTRL_MUXNEG_PA09 ADC_INPUTCTRL_MUXPOS_AIN7 
#define DAC_RES_BITS        (10)
 
#define DAC_NUMOF           (1)
 
#define RTT_MAX_VALUE       (0xffffffff)
#define RTT_CLOCK_FREQUENCY (32768U)                      /* in Hz */
#define RTT_MIN_FREQUENCY   (RTT_CLOCK_FREQUENCY / 1024U)  /* in Hz */
#define RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY)         /* in Hz */
static const gpio_t rtc_tamper_pins[RTC_NUM_OF_TAMPERS] = {
    GPIO_PIN(PA, 8), GPIO_PIN(PA, 9), GPIO_PIN(PA, 16),
    GPIO_PIN(PA, 17)
};
 
struct sam0_aux_cfg_mapping {
    /* config word 0 */
    uint32_t secure_region_unlock       :  3; 
    uint32_t non_secure_region_unlock   :  3; 
    uint32_t reserved_0                 :  1; 
    uint32_t bod33_level                :  6; 
    uint32_t bod33_disable              :  1; 
    uint32_t bod33_action               :  2; 
    const uint32_t bod12_calibration    :  9; 
    uint32_t wdt_run_standby            :  1; 
    uint32_t wdt_enable                 :  1; 
    uint32_t wdt_always_on              :  1; 
    uint32_t wdt_period                 :  4; 
    /* config word 1 */
    uint32_t wdt_window                 :  4; 
    uint32_t wdt_ewoffset               :  4; 
    uint32_t wdt_window_enable          :  1; 
    uint32_t bod33_hysteresis           :  1; 
    uint32_t reserved_1                 :  1; 
    uint32_t ram_execute_never          :  1; 
    uint32_t data_execute_never         :  1; 
    uint32_t reserved_2                 : 19; 
    /* config word 2 */
    uint32_t secure_flash_as_size       :  8; 
    uint32_t nsc_size                   :  6; 
    uint32_t reserved_3                 :  2; 
    uint32_t secure_flash_data_size     :  4; 
    uint32_t reserved_4                 :  4; 
    uint32_t secure_ram_size            :  7; 
    uint32_t reserved_5                 :  1; 
    /* config word 3 */
    uint32_t user_row_write_enable      :  1; 
    uint32_t reserved_6                 : 31; 
    /* config word 4 */
    uint32_t nonsec_a;            
    /* config word 5 */
    uint32_t nonsec_b;            
    /* config word 6 */
    uint32_t nonsec_c;            
    /* config word 7 */
    uint32_t user_crc;            
};
 
#ifdef __cplusplus
}
#endif