periph_conf.h
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1 /*
2  * Copyright (C) 2018 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
21 /* Add specific clock configuration (HSE, LSE) for this board here */
22 #ifndef CONFIG_BOARD_HAS_LSE
23 #define CONFIG_BOARD_HAS_LSE 1
24 #endif
25 
26 #include "periph_cpu.h"
27 #include "clk_conf.h"
28 #include "cfg_rtt_default.h"
29 #include "cfg_usb_otg_fs.h"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
39 static const timer_conf_t timer_config[] = {
40  {
41  .dev = TIM5,
42  .max = 0xffffffff,
43  .rcc_mask = RCC_APB1ENR1_TIM5EN,
44  .bus = APB1,
45  .irqn = TIM5_IRQn
46  }
47 };
48 
49 #define TIMER_0_ISR isr_tim5
50 
51 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
58 static const uart_conf_t uart_config[] = {
59  {
60  .dev = USART2,
61  .rcc_mask = RCC_APB1ENR1_USART2EN,
62  .rx_pin = GPIO_PIN(PORT_D, 6),
63  .tx_pin = GPIO_PIN(PORT_D, 5),
64  .rx_af = GPIO_AF7,
65  .tx_af = GPIO_AF7,
66  .bus = APB1,
67  .irqn = USART2_IRQn,
68  .type = STM32_USART,
69  .clk_src = 0, /* Use APB clock */
70 #ifdef UART_USE_DMA
71  .dma_stream = 6,
72  .dma_chan = 4
73 #endif
74  }
75 };
76 
77 #define UART_0_ISR (isr_usart2)
78 
79 #define UART_NUMOF ARRAY_SIZE(uart_config)
111 static const adc_conf_t adc_config[] = {
112  {GPIO_PIN(PORT_A, 0), 0, 5}, /*< ADC12_IN5 */
113  {GPIO_PIN(PORT_A, 5), 0, 10}, /*< ADC12_IN10 */
114  {GPIO_PIN(PORT_A, 1), 0, 6}, /*< ADC12_IN6 */
115  {GPIO_PIN(PORT_A, 2), 0, 7}, /*< ADC12_IN7 */
116  {GPIO_PIN(PORT_A, 3), 0, 8}, /*< ADC12_IN8 */
117  {GPIO_UNDEF, 0, 18}, /* VBAT */
118 };
119 
123 #define VBAT_ADC ADC_LINE(5)
124 
128 #define ADC_NUMOF ARRAY_SIZE(adc_config)
149 static const pwm_conf_t pwm_config[] = {
150  {
151  .dev = TIM2,
152  .rcc_mask = RCC_APB1ENR1_TIM2EN,
153  .chan = { { .pin = GPIO_PIN(PORT_A, 5), .cc_chan = 0},
154  { .pin = GPIO_PIN(PORT_A, 1), .cc_chan = 1},
155  { .pin = GPIO_PIN(PORT_A, 2), .cc_chan = 2},
156  { .pin = GPIO_PIN(PORT_A, 3), .cc_chan = 3} },
157  .af = GPIO_AF1,
158  .bus = APB1
159  },
160  {
161  .dev = TIM1,
162  .rcc_mask = RCC_APB2ENR_TIM1EN,
163  .chan = { { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 1},
164  { .pin = GPIO_PIN(PORT_E, 13), .cc_chan = 2},
165  { .pin = GPIO_PIN(PORT_E, 14), .cc_chan = 3},
166  { .pin = GPIO_UNDEF, .cc_chan = 0} },
167  .af = GPIO_AF1,
168  .bus = APB2
169  }
170 };
171 
172 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
175 #ifdef __cplusplus
176 }
177 #endif
178 
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:111
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ STM32_USART
STM32 USART module type.
Definition: cpu_uart.h:37
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
PWM device configuration.
mini_timer_t * dev
Timer used.
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218