cfg_usb_otg_fs_u5.h
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1 /*
2  * Copyright (C) 2019 Koen Zandberg
3  * 2023 Gunar Schorcht
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
10 #pragma once
11 
23 #include "periph_cpu.h"
24 #include "usbdev_synopsys_dwc2.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 #define DWC2_USB_OTG_FS_ENABLED
34 
39  {
40  .periph = USB_OTG_FS_BASE,
41  .type = DWC2_USB_OTG_FS,
43  .rcc_mask = RCC_AHB2ENR1_OTGEN,
44  .irqn = OTG_FS_IRQn,
45  .ahb = AHB2,
46  .dm = GPIO_PIN(PORT_A, 11),
47  .dp = GPIO_PIN(PORT_A, 12),
48  .af = GPIO_AF10,
49  }
50 };
51 
55 #define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
56 
57 #ifdef __cplusplus
58 }
59 #endif
60 
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG FS configuration.
@ GPIO_AF10
use alternate function 10
Definition: cpu_gpio.h:112
USB OTG configuration.
uintptr_t periph
USB peripheral base address.
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_BUILTIN
on-chip FS PHY
@ DWC2_USB_OTG_FS
Full speed peripheral.