periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2020 Inria
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
18 #include "periph_cpu.h"
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
28 #ifndef CLOCK_CORECLOCK
29 #define CLOCK_CORECLOCK MHZ(120)
30 #endif
37 #define EXTERNAL_OSC32_SOURCE 0
38 #define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE 1
45 #define USE_VREG_BUCK (1)
46 
51 static const tc32_conf_t timer_config[] = {
52  { /* Timer 0 - System Clock */
53  .dev = TC0,
54  .irq = TC0_IRQn,
55  .mclk = &MCLK->APBAMASK.reg,
56  .mclk_mask = MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1,
57  .gclk_id = TC0_GCLK_ID,
58  .gclk_src = SAM0_GCLK_TIMER,
59  .flags = TC_CTRLA_MODE_COUNT32,
60  },
61  { /* Timer 1 */
62  .dev = TC2,
63  .irq = TC2_IRQn,
64  .mclk = &MCLK->APBBMASK.reg,
65  .mclk_mask = MCLK_APBBMASK_TC2 | MCLK_APBBMASK_TC3,
66  .gclk_id = TC2_GCLK_ID,
67  .gclk_src = SAM0_GCLK_TIMER,
68  .flags = TC_CTRLA_MODE_COUNT32,
69  }
70 };
71 
72 /* Timer 0 configuration */
73 #define TIMER_0_CHANNELS 2
74 #define TIMER_0_ISR isr_tc0
75 
76 /* Timer 1 configuration */
77 #define TIMER_1_CHANNELS 2
78 #define TIMER_1_ISR isr_tc2
79 
80 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
87 static const uart_conf_t uart_config[] = {
88  { /* Virtual COM Port */
89  .dev = &SERCOM5->USART,
90  .rx_pin = GPIO_PIN(PB, 16),
91  .tx_pin = GPIO_PIN(PB, 17),
92 #ifdef MODULE_SAM0_PERIPH_UART_HW_FC
93  .rts_pin = GPIO_UNDEF,
94  .cts_pin = GPIO_UNDEF,
95 #endif
96  .mux = GPIO_MUX_C,
97  .rx_pad = UART_PAD_RX_1,
98  .tx_pad = UART_PAD_TX_0,
99  .flags = UART_FLAG_NONE,
100  .gclk_src = SAM0_GCLK_PERIPH,
101  }
102 };
103 
104 /* interrupt function name mapping */
105 #define UART_0_ISR isr_sercom5_2
106 #define UART_0_ISR_TX isr_sercom5_0
107 
108 #define UART_NUMOF ARRAY_SIZE(uart_config)
115 #define PWM_0_EN 1
116 
117 #if PWM_0_EN
118 /* PWM0 channels */
119 static const pwm_conf_chan_t pwm_chan0_config[] = {
120  /* GPIO pin, MUX value, TCC channel */
121  { GPIO_PIN(PA, 22), GPIO_MUX_G, 2 },
122 };
123 #endif
124 
125 /* PWM device configuration */
126 static const pwm_conf_t pwm_config[] = {
127 #if PWM_0_EN
128  { .tim = TCC_CONFIG(TCC0),
129  .chan = pwm_chan0_config,
130  .chan_numof = ARRAY_SIZE(pwm_chan0_config),
131  .gclk_src = SAM0_GCLK_PERIPH,
132  },
133 #endif
134 };
135 
136 /* number of devices that are actually defined */
137 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
144 static const spi_conf_t spi_config[] = {
145  {
146  .dev = &(SERCOM1->SPI),
147  .miso_pin = GPIO_PIN(PB, 22),
148  .mosi_pin = GPIO_PIN(PB, 23),
149  .clk_pin = GPIO_PIN(PA, 17),
150  .miso_mux = GPIO_MUX_C,
151  .mosi_mux = GPIO_MUX_C,
152  .clk_mux = GPIO_MUX_C,
153  .miso_pad = SPI_PAD_MISO_2,
154  .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
155  .gclk_src = SAM0_GCLK_PERIPH,
156 #ifdef MODULE_PERIPH_DMA
157  .tx_trigger = SERCOM1_DMAC_ID_TX,
158  .rx_trigger = SERCOM1_DMAC_ID_RX,
159 #endif
160  },
161  { /* Connected to TFT display */
162  .dev = &(SERCOM4->SPI),
163  .miso_pin = GPIO_PIN(PB, 12),
164  .mosi_pin = GPIO_PIN(PB, 15),
165  .clk_pin = GPIO_PIN(PB, 13),
166  .miso_mux = GPIO_MUX_C,
167  .mosi_mux = GPIO_MUX_C,
168  .clk_mux = GPIO_MUX_C,
169  .miso_pad = SPI_PAD_MISO_0,
170  .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
171  .gclk_src = SAM0_GCLK_PERIPH,
172 #ifdef MODULE_PERIPH_DMA
173  .tx_trigger = SERCOM4_DMAC_ID_TX,
174  .rx_trigger = SERCOM4_DMAC_ID_RX,
175 #endif
176  },
177  { /* Connected to PDM Mic */
178  .dev = &(SERCOM3->SPI),
179  .miso_pin = GPIO_PIN(PA, 18),
180  .mosi_pin = GPIO_PIN(PA, 19),
181  .clk_pin = GPIO_PIN(PA, 16),
182  .miso_mux = GPIO_MUX_D,
183  .mosi_mux = GPIO_MUX_D,
184  .clk_mux = GPIO_MUX_D,
185  .miso_pad = SPI_PAD_MISO_2,
186  .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
187  .gclk_src = SAM0_GCLK_PERIPH,
188 #ifdef MODULE_PERIPH_DMA
189  .tx_trigger = SERCOM4_DMAC_ID_TX,
190  .rx_trigger = SERCOM4_DMAC_ID_RX,
191 #endif
192  },
193 #ifdef MODULE_PERIPH_SPI_ON_QSPI
194  { /* QSPI in SPI mode */
195  .dev = QSPI,
196  .miso_pin = SAM0_QSPI_PIN_DATA_1,
197  .mosi_pin = SAM0_QSPI_PIN_DATA_0,
198  .clk_pin = SAM0_QSPI_PIN_CLK,
199  .miso_mux = SAM0_QSPI_MUX,
200  .mosi_mux = SAM0_QSPI_MUX,
201  .clk_mux = SAM0_QSPI_MUX,
202  .miso_pad = SPI_PAD_MISO_0, /* unused */
203  .mosi_pad = SPI_PAD_MOSI_0_SCK_1, /* unused */
204  .gclk_src = SAM0_GCLK_MAIN, /* unused */
205 #ifdef MODULE_PERIPH_DMA
206  .tx_trigger = QSPI_DMAC_ID_TX,
207  .rx_trigger = QSPI_DMAC_ID_RX,
208 #endif
209  },
210 #endif
211 };
212 
213 #define SPI_NUMOF ARRAY_SIZE(spi_config)
220 static const i2c_conf_t i2c_config[] = {
221  {
222  .dev = &(SERCOM2->I2CM),
223  .speed = I2C_SPEED_NORMAL,
224  .scl_pin = GPIO_PIN(PA, 13),
225  .sda_pin = GPIO_PIN(PA, 12),
226  .mux = GPIO_MUX_C,
227  .gclk_src = SAM0_GCLK_PERIPH,
228  .flags = I2C_FLAG_NONE
229  },
230 };
231 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
238 #ifndef RTT_FREQUENCY
239 #define RTT_FREQUENCY (32768U)
240 #endif
247 static const sam0_common_usb_config_t sam_usbdev_config[] = {
248  {
249  .dm = GPIO_PIN(PA, 24),
250  .dp = GPIO_PIN(PA, 25),
251  .d_mux = GPIO_MUX_H,
252  .device = &USB->DEVICE,
253  .gclk_src = SAM0_GCLK_48MHZ,
254  }
255 };
263 /* ADC Default values */
264 #define ADC_GCLK_SRC SAM0_GCLK_PERIPH
265 #define ADC_PRESCALER ADC_CTRLA_PRESCALER_DIV8
266 
267 #define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG(0x18u)
268 #define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
269 
270 static const adc_conf_chan_t adc_channels[] = {
271  /* port, pin, muxpos, dev */
272  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA05, .dev = ADC0 }, /* A1 */
273  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB08, .dev = ADC0 }, /* A2 */
274  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB09, .dev = ADC0 }, /* A3 */
275  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA04, .dev = ADC0 }, /* A4 */
276  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA06, .dev = ADC0 }, /* A5 */
277  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB01, .dev = ADC0 }, /* A6 - VMEAS */
278  { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB04, .dev = ADC1 }, /* A7 - Light sensor */
279 };
280 
281 #define ADC_NUMOF ARRAY_SIZE(adc_channels)
288 #define DAC_CLOCK SAM0_GCLK_TIMER
293 #define DAC_VREF DAC_CTRLB_REFSEL_VREFPU
296 #ifdef __cplusplus
297 }
298 #endif
299 
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:65
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:36
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:218
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition: container.h:82
static const gpio_t adc_channels[]
Static array with declared ADC channels.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
@ UART_PAD_RX_1
select pad 1
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_2
use pad 2 for MISO line
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0
select pad 0
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_G
select peripheral function G
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_3_SCK_1
use pad 3 for MOSI, pad 1 for SCK
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition: periph_cpu.h:73
#define ADC0_INPUTCTRL_MUXPOS_PA04
Alias for AIN4.
Definition: periph_cpu.h:129
#define SAM0_QSPI_PIN_CLK
Clock
Definition: periph_cpu.h:268
#define ADC1_INPUTCTRL_MUXPOS_PB04
Alias for AIN6.
Definition: periph_cpu.h:148
#define ADC0_INPUTCTRL_MUXPOS_PA05
Alias for AIN5.
Definition: periph_cpu.h:130
#define ADC0_INPUTCTRL_MUXPOS_PB01
Alias for AIN13.
Definition: periph_cpu.h:138
#define SAM0_QSPI_PIN_DATA_0
D0 / MOSI
Definition: periph_cpu.h:270
#define SAM0_QSPI_PIN_DATA_1
D1 / MISO
Definition: periph_cpu.h:271
#define ADC0_INPUTCTRL_MUXPOS_PB08
Alias for AIN2.
Definition: periph_cpu.h:127
#define SAM0_QSPI_MUX
QSPI mux
Definition: periph_cpu.h:274
#define ADC0_INPUTCTRL_MUXPOS_PB09
Alias for AIN3.
Definition: periph_cpu.h:128
#define ADC0_INPUTCTRL_MUXPOS_PA06
Alias for AIN6.
Definition: periph_cpu.h:131
#define SAM0_GCLK_PERIPH
12-48 MHz (DFLL) clock
Definition: periph_cpu.h:81
@ SAM0_GCLK_TIMER
4/8MHz clock for timers
Definition: periph_cpu.h:70
@ SAM0_GCLK_48MHZ
48MHz clock
Definition: periph_cpu.h:72
ADC Channel Configuration.
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
PWM channel configuration data structure.
PWM device configuration.
tc_tcc_cfg_t tim
timer configuration
USB peripheral parameters.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218