periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2017 Inria
3  * SPDX-FileCopyrightText: 2017 OTA keys
4  * SPDX-License-Identifier: LGPL-2.1-only
5  */
6 
7 #pragma once
8 
20 #include "periph_cpu.h"
21 #include "clk_conf.h"
22 #include "cfg_timer_tim2.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 static const uart_conf_t uart_config[] = {
33  {
34  .dev = USART1,
35  .rcc_mask = RCC_APB2ENR_USART1EN,
36  .rx_pin = GPIO_PIN(PORT_A, 15),
37  .tx_pin = GPIO_PIN(PORT_A, 2),
38  .rx_af = GPIO_AF1,
39  .tx_af = GPIO_AF1,
40  .bus = APB2,
41  .irqn = USART1_IRQn
42  }
43 };
44 
45 #define UART_0_ISR (isr_usart1)
46 
47 #define UART_NUMOF ARRAY_SIZE(uart_config)
54 static const pwm_conf_t pwm_config[] = {
55  {
56  .dev = TIM1,
57  .rcc_mask = RCC_APB2ENR_TIM1EN,
58  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
59  { .pin = GPIO_UNDEF, .cc_chan = 0 },
60  { .pin = GPIO_UNDEF, .cc_chan = 0 },
61  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
62  .af = GPIO_AF2,
63  .bus = APB2
64  },
65  {
66  .dev = TIM14,
67  .rcc_mask = RCC_APB1ENR_TIM14EN,
68  .chan = { { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 0 },
69  { .pin = GPIO_UNDEF, .cc_chan = 0 },
70  { .pin = GPIO_UNDEF, .cc_chan = 0 },
71  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
72  .af = GPIO_AF0,
73  .bus = APB1
74  },
75  {
76  .dev = TIM3,
77  .rcc_mask = RCC_APB1ENR_TIM3EN,
78  .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
79  { .pin = GPIO_UNDEF, .cc_chan = 0 },
80  { .pin = GPIO_UNDEF, .cc_chan = 0 },
81  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
82  .af = GPIO_AF1,
83  .bus = APB1
84  },
85 };
86 
87 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
94 static const spi_conf_t spi_config[] = {
95  {
96  .dev = SPI1,
97  .mosi_pin = GPIO_PIN(PORT_B, 5),
98  .miso_pin = GPIO_PIN(PORT_B, 4),
99  .sclk_pin = GPIO_PIN(PORT_B, 3),
100  .cs_pin = SPI_CS_UNDEF,
101  .mosi_af = GPIO_AF0,
102  .miso_af = GPIO_AF0,
103  .sclk_af = GPIO_AF0,
104  .cs_af = GPIO_AF0,
105  .rccmask = RCC_APB2ENR_SPI1EN,
106  .apbbus = APB2
107  }
108 };
109 
110 #define SPI_NUMOF ARRAY_SIZE(spi_config)
117 static const adc_conf_t adc_config[] = {
118  { GPIO_PIN(PORT_A, 0), 0 },
119  { GPIO_PIN(PORT_A, 1), 1 },
120  { GPIO_PIN(PORT_A, 3), 3 },
121  { GPIO_PIN(PORT_A, 4), 4 },
122  { GPIO_PIN(PORT_A, 7), 7 },
123  { GPIO_UNDEF, 18 }, /* VBAT */
124 };
125 
126 #define VBAT_ADC ADC_LINE(5)
127 #define ADC_NUMOF ARRAY_SIZE(adc_config)
130 #ifdef __cplusplus
131 }
132 #endif
133 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:247
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:218
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF0
use alternate function 0
Definition: cpu_gpio.h:101
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218