periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2015 Freie Universität Berlin
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
18 /* HSE available on this board */
19 #ifndef CONFIG_BOARD_HAS_HSE
20 #define CONFIG_BOARD_HAS_HSE 1
21 #endif
22 
23 /* This board provides an LSE */
24 #ifndef CONFIG_BOARD_HAS_LSE
25 #define CONFIG_BOARD_HAS_LSE 1
26 #endif
27 
28 #include "periph_cpu.h"
29 #include "clk_conf.h"
30 #include "cfg_i2c1_pb8_pb9.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
40 static const dma_conf_t dma_config[] = {
41  { .stream = 1 },
42  { .stream = 2 },
43 };
44 
45 #define DMA_SHARED_ISR_0 isr_dma1_ch2_3_dma2_ch1_2
46 #define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */
47 
48 #define DMA_NUMOF ARRAY_SIZE(dma_config)
55 static const timer_conf_t timer_config[] = {
56  {
57  .dev = TIM1,
58  .max = 0x0000ffff,
59  .rcc_mask = RCC_APB2ENR_TIM1EN,
60  .bus = APB2,
61  .irqn = TIM1_CC_IRQn
62  }
63 };
64 
65 #define TIMER_0_ISR isr_tim1_cc
66 
67 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
74 static const uart_conf_t uart_config[] = {
75  {
76  .dev = USART2,
77  .rcc_mask = RCC_APB1ENR_USART2EN,
78  .rx_pin = GPIO_PIN(PORT_A, 3),
79  .tx_pin = GPIO_PIN(PORT_A, 2),
80  .rx_af = GPIO_AF1,
81  .tx_af = GPIO_AF1,
82  .bus = APB1,
83  .irqn = USART2_IRQn,
84 #ifdef MODULE_PERIPH_DMA
85  .dma = 0,
86  .dma_chan = 0x9,
87 #endif
88  },
89  {
90  .dev = USART1,
91  .rcc_mask = RCC_APB2ENR_USART1EN,
92  .rx_pin = GPIO_PIN(PORT_A, 10),
93  .tx_pin = GPIO_PIN(PORT_A, 9),
94  .rx_af = GPIO_AF1,
95  .tx_af = GPIO_AF1,
96  .bus = APB2,
97  .irqn = USART1_IRQn,
98 #ifdef MODULE_PERIPH_DMA
99  .dma = 0,
100  .dma_chan = 0x8,
101 #endif
102  },
103  {
104  .dev = USART3,
105  .rcc_mask = RCC_APB1ENR_USART3EN,
106  .rx_pin = GPIO_PIN(PORT_C, 11),
107  .tx_pin = GPIO_PIN(PORT_C, 10),
108  .rx_af = GPIO_AF1,
109  .tx_af = GPIO_AF1,
110  .bus = APB1,
111  .irqn = USART3_8_IRQn,
112 #ifdef MODULE_PERIPH_DMA
113  .dma = 0,
114  .dma_chan = 0xA,
115 #endif
116  },
117 };
118 
119 #define UART_0_ISR (isr_usart2)
120 #define UART_1_ISR (isr_usart1)
121 #define UART_2_ISR (isr_usart3_8)
122 
123 #define UART_NUMOF ARRAY_SIZE(uart_config)
130 static const spi_conf_t spi_config[] = {
131  {
132  .dev = SPI1,
133  .mosi_pin = GPIO_PIN(PORT_A, 7),
134  .miso_pin = GPIO_PIN(PORT_A, 6),
135  .sclk_pin = GPIO_PIN(PORT_A, 5),
136  .cs_pin = GPIO_PIN(PORT_B, 6),
137  .mosi_af = GPIO_AF0,
138  .miso_af = GPIO_AF0,
139  .sclk_af = GPIO_AF0,
140  .cs_af = GPIO_AF0,
141  .rccmask = RCC_APB2ENR_SPI1EN,
142  .apbbus = APB2,
143 #ifdef MODULE_PERIPH_DMA
144  .tx_dma = 1,
145  .tx_dma_chan = 0,
146  .rx_dma = 0,
147  .rx_dma_chan = 0,
148 #endif
149  }
150 };
151 
152 #define SPI_NUMOF ARRAY_SIZE(spi_config)
159 static const pwm_conf_t pwm_config[] = {
160  {
161  .dev = TIM2,
162  .rcc_mask = RCC_APB1ENR_TIM2EN,
163  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
164  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
165  { .pin = GPIO_PIN(PORT_B, 11) , .cc_chan = 3 },
166  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
167  .af = GPIO_AF2,
168  .bus = APB1
169  },
170  {
171  .dev = TIM3,
172  .rcc_mask = RCC_APB1ENR_TIM3EN,
173  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
174  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
175  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
176  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
177  .af = GPIO_AF0,
178  .bus = APB1
179  }
180 };
181 
182 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
189 static const adc_conf_t adc_config[] = {
190  { GPIO_PIN(PORT_A, 0), 0 },
191  { GPIO_PIN(PORT_A, 1), 1 },
192  { GPIO_PIN(PORT_A, 4), 4 },
193  { GPIO_PIN(PORT_B, 0), 8 },
194  { GPIO_PIN(PORT_C, 1), 11 },
195  { GPIO_PIN(PORT_C, 0), 10 },
196  { GPIO_UNDEF, 18 }, /* VBAT */
197 };
198 
199 #define VBAT_ADC ADC_LINE(6)
200 #define ADC_NUMOF ARRAY_SIZE(adc_config)
203 #ifdef __cplusplus
204 }
205 #endif
206 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:36
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:247
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:218
Common configuration for STM32 I2C.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF0
use alternate function 0
Definition: cpu_gpio.h:101
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218