periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2016 Inria
3  * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4  * SPDX-License-Identifier: LGPL-2.1-only
5  */
6 
7 #pragma once
8 
20 /* This board provides an LSE */
21 #ifndef CONFIG_BOARD_HAS_LSE
22 #define CONFIG_BOARD_HAS_LSE 1
23 #endif
24 
25 /* This board provides an HSE */
26 #ifndef CONFIG_BOARD_HAS_HSE
27 #define CONFIG_BOARD_HAS_HSE 1
28 #endif
29 
30 #include "periph_cpu.h"
31 #include "clk_conf.h"
32 #include "cfg_i2c1_pb8_pb9.h"
33 #include "cfg_timer_tim5.h"
34 #include "cfg_usb_otg_fs.h"
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
44 static const dma_conf_t dma_config[] = {
45  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
46  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
47 };
48 
49 #define DMA_0_ISR isr_dma2_stream3
50 #define DMA_1_ISR isr_dma2_stream2
51 
52 #define DMA_NUMOF ARRAY_SIZE(dma_config)
59 static const uart_conf_t uart_config[] = {
60  {
61  .dev = USART3,
62  .rcc_mask = RCC_APB1ENR_USART3EN,
63  .rx_pin = GPIO_PIN(PORT_D, 9),
64  .tx_pin = GPIO_PIN(PORT_D, 8),
65  .rx_af = GPIO_AF7,
66  .tx_af = GPIO_AF7,
67  .bus = APB1,
68  .irqn = USART3_IRQn,
69 #ifdef MODULE_PERIPH_DMA
70  .dma = DMA_STREAM_UNDEF,
71  .dma_chan = UINT8_MAX,
72 #endif
73  },
74  {
75  .dev = USART6,
76  .rcc_mask = RCC_APB2ENR_USART6EN,
77  .rx_pin = GPIO_PIN(PORT_G, 9),
78  .tx_pin = GPIO_PIN(PORT_G, 14),
79  .rx_af = GPIO_AF8,
80  .tx_af = GPIO_AF8,
81  .bus = APB2,
82  .irqn = USART6_IRQn,
83 #ifdef MODULE_PERIPH_DMA
84  .dma = DMA_STREAM_UNDEF,
85  .dma_chan = UINT8_MAX,
86 #endif
87  },
88  {
89  .dev = USART2,
90  .rcc_mask = RCC_APB2ENR_USART1EN,
91  .rx_pin = GPIO_PIN(PORT_D, 6),
92  .tx_pin = GPIO_PIN(PORT_D, 5),
93  .rx_af = GPIO_AF7,
94  .tx_af = GPIO_AF7,
95  .bus = APB2,
96  .irqn = USART2_IRQn,
97 #ifdef MODULE_PERIPH_DMA
98  .dma = DMA_STREAM_UNDEF,
99  .dma_chan = UINT8_MAX,
100 #endif
101  },
102 };
103 
104 #define UART_0_ISR (isr_usart3)
105 #define UART_1_ISR (isr_usart6)
106 #define UART_2_ISR (isr_usart2)
107 
108 #define UART_NUMOF ARRAY_SIZE(uart_config)
115 static const pwm_conf_t pwm_config[] = {
116  {
117  .dev = TIM1,
118  .rcc_mask = RCC_APB2ENR_TIM1EN,
119  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
120  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
121  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
122  { .pin = GPIO_UNDEF, .cc_chan = 0} },
123  .af = GPIO_AF1,
124  .bus = APB2
125  },
126  {
127  .dev = TIM4,
128  .rcc_mask = RCC_APB1ENR_TIM4EN,
129  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
130  { .pin = GPIO_UNDEF, .cc_chan = 0},
131  { .pin = GPIO_UNDEF, .cc_chan = 0},
132  { .pin = GPIO_UNDEF, .cc_chan = 0} },
133  .af = GPIO_AF2,
134  .bus = APB1
135  },
136 };
137 
138 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
145 static const spi_conf_t spi_config[] = {
146  {
147  .dev = SPI1,
148  .mosi_pin = GPIO_PIN(PORT_A, 7),
149  .miso_pin = GPIO_PIN(PORT_A, 6),
150  .sclk_pin = GPIO_PIN(PORT_A, 5),
151  .cs_pin = GPIO_PIN(PORT_A, 4),
152  .mosi_af = GPIO_AF5,
153  .miso_af = GPIO_AF5,
154  .sclk_af = GPIO_AF5,
155  .cs_af = GPIO_AF5,
156  .rccmask = RCC_APB2ENR_SPI1EN,
157  .apbbus = APB2,
158 #ifdef MODULE_PERIPH_DMA
159  .tx_dma = 0,
160  .tx_dma_chan = 3,
161  .rx_dma = 1,
162  .rx_dma_chan = 3,
163 #endif
164  }
165 };
166 
167 #define SPI_NUMOF ARRAY_SIZE(spi_config)
180 static const adc_conf_t adc_config[] = {
181  {GPIO_PIN(PORT_A, 3), 0, 3},
182  {GPIO_PIN(PORT_C, 0), 0, 10},
183  {GPIO_PIN(PORT_C, 3), 0, 13},
184  {GPIO_PIN(PORT_C, 1), 0, 11},
185  {GPIO_PIN(PORT_C, 4), 0, 14},
186  {GPIO_PIN(PORT_C, 5), 0, 15},
187  {GPIO_UNDEF, 0, 18}, /* VBAT */
188 };
189 
190 #define VBAT_ADC ADC_LINE(6)
191 #define ADC_NUMOF ARRAY_SIZE(adc_config)
194 #ifdef __cplusplus
195 }
196 #endif
197 
@ PORT_G
port G
Definition: periph_cpu.h:52
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:247
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:218
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218