periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2016 Inria
3  * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4  * SPDX-License-Identifier: LGPL-2.1-only
5  */
6 
7 #pragma once
8 
20 /* This board provides an LSE */
21 #ifndef CONFIG_BOARD_HAS_LSE
22 #define CONFIG_BOARD_HAS_LSE 1
23 #endif
24 
25 /* This board provides an HSE */
26 #ifndef CONFIG_BOARD_HAS_HSE
27 #define CONFIG_BOARD_HAS_HSE 1
28 #endif
29 
30 #include "periph_cpu.h"
31 #include "clk_conf.h"
32 #include "cfg_i2c1_pb8_pb9.h"
33 #include "cfg_rtt_default.h"
34 #include "cfg_timer_tim5.h"
35 #include "cfg_usb_otg_fs.h"
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
45 static const dma_conf_t dma_config[] = {
46  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
47  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
48  { .stream = 3 }, /* DMA1 Stream 3 - UART3_TX */
49  { .stream = 15 }, /* DMA2 Stream 7 - UART6_TX */
50  { .stream = 6 }, /* DMA1 Stream 6 - UART2_TX */
51 };
52 
53 #define DMA_0_ISR isr_dma2_stream3
54 #define DMA_1_ISR isr_dma2_stream2
55 #define DMA_2_ISR isr_dma1_stream3
56 #define DMA_3_ISR isr_dma2_stream7
57 #define DMA_4_ISR isr_dma1_stream6
58 
59 #define DMA_NUMOF ARRAY_SIZE(dma_config)
66 static const uart_conf_t uart_config[] = {
67  {
68  .dev = USART3,
69  .rcc_mask = RCC_APB1ENR_USART3EN,
70  .rx_pin = GPIO_PIN(PORT_D, 9),
71  .tx_pin = GPIO_PIN(PORT_D, 8),
72  .rx_af = GPIO_AF7,
73  .tx_af = GPIO_AF7,
74  .bus = APB1,
75  .irqn = USART3_IRQn,
76 #ifdef MODULE_PERIPH_DMA
77  .dma = 2,
78  .dma_chan = 4,
79 #endif
80  },
81  {
82  .dev = USART6,
83  .rcc_mask = RCC_APB2ENR_USART6EN,
84  .rx_pin = GPIO_PIN(PORT_G, 9),
85  .tx_pin = GPIO_PIN(PORT_G, 14),
86  .rx_af = GPIO_AF8,
87  .tx_af = GPIO_AF8,
88  .bus = APB2,
89  .irqn = USART6_IRQn,
90 #ifdef MODULE_PERIPH_DMA
91  .dma = 3,
92  .dma_chan = 5,
93 #endif
94  },
95  {
96  .dev = USART2,
97  .rcc_mask = RCC_APB1ENR_USART2EN,
98  .rx_pin = GPIO_PIN(PORT_D, 6),
99  .tx_pin = GPIO_PIN(PORT_D, 5),
100  .rx_af = GPIO_AF7,
101  .tx_af = GPIO_AF7,
102  .bus = APB1,
103  .irqn = USART2_IRQn,
104 #ifdef MODULE_PERIPH_DMA
105  .dma = 4,
106  .dma_chan = 4,
107 #endif
108  },
109 };
110 
111 #define UART_0_ISR (isr_usart3)
112 #define UART_1_ISR (isr_usart6)
113 #define UART_2_ISR (isr_usart2)
114 
115 #define UART_NUMOF ARRAY_SIZE(uart_config)
122 static const pwm_conf_t pwm_config[] = {
123  {
124  .dev = TIM1,
125  .rcc_mask = RCC_APB2ENR_TIM1EN,
126  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
127  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
128  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
129  { .pin = GPIO_UNDEF, .cc_chan = 0} },
130  .af = GPIO_AF1,
131  .bus = APB2
132  },
133  {
134  .dev = TIM4,
135  .rcc_mask = RCC_APB1ENR_TIM4EN,
136  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
137  { .pin = GPIO_UNDEF, .cc_chan = 0},
138  { .pin = GPIO_UNDEF, .cc_chan = 0},
139  { .pin = GPIO_UNDEF, .cc_chan = 0} },
140  .af = GPIO_AF2,
141  .bus = APB1
142  },
143 };
144 
145 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
152 static const spi_conf_t spi_config[] = {
153  {
154  .dev = SPI1,
155  .mosi_pin = GPIO_PIN(PORT_A, 7),
156  .miso_pin = GPIO_PIN(PORT_A, 6),
157  .sclk_pin = GPIO_PIN(PORT_A, 5),
158  .cs_pin = GPIO_PIN(PORT_A, 4),
159  .mosi_af = GPIO_AF5,
160  .miso_af = GPIO_AF5,
161  .sclk_af = GPIO_AF5,
162  .cs_af = GPIO_AF5,
163  .rccmask = RCC_APB2ENR_SPI1EN,
164  .apbbus = APB2,
165 #ifdef MODULE_PERIPH_DMA
166  .tx_dma = 0,
167  .tx_dma_chan = 3,
168  .rx_dma = 1,
169  .rx_dma_chan = 3,
170 #endif
171  }
172 };
173 
174 #define SPI_NUMOF ARRAY_SIZE(spi_config)
187 static const adc_conf_t adc_config[] = {
188  {GPIO_PIN(PORT_A, 3), 0, 3},
189  {GPIO_PIN(PORT_C, 0), 0, 10},
190  {GPIO_PIN(PORT_C, 3), 0, 13},
191  {GPIO_PIN(PORT_C, 1), 0, 11},
192  {GPIO_PIN(PORT_C, 4), 0, 14},
193  {GPIO_PIN(PORT_C, 5), 0, 15},
194  {GPIO_UNDEF, 0, 18}, /* VBAT */
195 };
196 
197 #define VBAT_ADC ADC_LINE(6)
198 #define ADC_NUMOF ARRAY_SIZE(adc_config)
205 #ifndef RTT_FREQUENCY
206 #define RTT_FREQUENCY (4096)
207 #endif
210 #ifdef __cplusplus
211 }
212 #endif
213 
@ PORT_G
port G
Definition: periph_cpu.h:52
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:247
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:218
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218