periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2016 Inria
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
18 /* This board provides an LSE */
19 #ifndef CONFIG_BOARD_HAS_LSE
20 #define CONFIG_BOARD_HAS_LSE 1
21 #endif
22 
23 /* This board provides an HSE */
24 #ifndef CONFIG_BOARD_HAS_HSE
25 #define CONFIG_BOARD_HAS_HSE 1
26 #endif
27 
28 #include "periph_cpu.h"
29 #include "clk_conf.h"
30 #include "cfg_i2c1_pb8_pb9.h"
31 #include "cfg_timer_tim5.h"
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
41 static const dma_conf_t dma_config[] = {
42  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
43  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
44  { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */
45  { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */
46  { .stream = 5 }, /* DMA1 Stream 5 - SPI3_TX */
47  { .stream = 0 }, /* DMA1 Stream 0 - SPI3_RX */
48 };
49 
50 #define DMA_0_ISR isr_dma2_stream3
51 #define DMA_1_ISR isr_dma2_stream2
52 #define DMA_2_ISR isr_dma1_stream4
53 #define DMA_3_ISR isr_dma1_stream3
54 #define DMA_4_ISR isr_dma1_stream5
55 #define DMA_5_ISR isr_dma1_stream0
56 
57 #define DMA_NUMOF ARRAY_SIZE(dma_config)
64 static const uart_conf_t uart_config[] = {
65  {
66  .dev = USART2,
67  .rcc_mask = RCC_APB1ENR_USART2EN,
68  .rx_pin = GPIO_PIN(PORT_A, 3),
69  .tx_pin = GPIO_PIN(PORT_A, 2),
70  .rx_af = GPIO_AF7,
71  .tx_af = GPIO_AF7,
72  .bus = APB1,
73  .irqn = USART2_IRQn,
74 #ifdef MODULE_PERIPH_DMA
75  .dma = DMA_STREAM_UNDEF,
76  .dma_chan = UINT8_MAX,
77 #endif
78  },
79  {
80  .dev = USART1,
81  .rcc_mask = RCC_APB2ENR_USART1EN,
82  .rx_pin = GPIO_PIN(PORT_A, 10),
83  .tx_pin = GPIO_PIN(PORT_A, 9),
84  .rx_af = GPIO_AF7,
85  .tx_af = GPIO_AF7,
86  .bus = APB2,
87  .irqn = USART1_IRQn,
88 #ifdef MODULE_PERIPH_DMA
89  .dma = DMA_STREAM_UNDEF,
90  .dma_chan = UINT8_MAX,
91 #endif
92  },
93  {
94  .dev = USART3,
95  .rcc_mask = RCC_APB1ENR_USART3EN,
96  .rx_pin = GPIO_PIN(PORT_C, 11),
97  .tx_pin = GPIO_PIN(PORT_C, 10),
98  .rx_af = GPIO_AF7,
99  .tx_af = GPIO_AF7,
100  .bus = APB1,
101  .irqn = USART3_IRQn,
102 #ifdef MODULE_PERIPH_DMA
103  .dma = DMA_STREAM_UNDEF,
104  .dma_chan = UINT8_MAX,
105 #endif
106  },
107 };
108 
109 #define UART_0_ISR (isr_usart2)
110 #define UART_1_ISR (isr_usart1)
111 #define UART_2_ISR (isr_usart3)
112 
113 #define UART_NUMOF ARRAY_SIZE(uart_config)
120 static const pwm_conf_t pwm_config[] = {
121  {
122  .dev = TIM2,
123  .rcc_mask = RCC_APB1ENR_TIM2EN,
124  .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
125  { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
126  { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
127  { .pin = GPIO_PIN(PORT_B, 2), .cc_chan = 3} },
128  .af = GPIO_AF1,
129  .bus = APB1
130  },
131  {
132  .dev = TIM8,
133  .rcc_mask = RCC_APB2ENR_TIM8EN,
134  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
135  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
136  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
137  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
138  .af = GPIO_AF3,
139  .bus = APB2
140  },
141 };
142 
143 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
150 static const qdec_conf_t qdec_config[] = {
151  {
152  .dev = TIM3,
153  .max = 0xffffffff,
154  .rcc_mask = RCC_APB1ENR_TIM3EN,
155  .chan = { { .pin = GPIO_PIN(PORT_A, 6), .cc_chan = 0 },
156  { .pin = GPIO_PIN(PORT_A, 7), .cc_chan = 1 } },
157  .af = GPIO_AF2,
158  .bus = APB1,
159  .irqn = TIM3_IRQn
160  },
161  {
162  .dev = TIM4,
163  .max = 0xffffffff,
164  .rcc_mask = RCC_APB1ENR_TIM4EN,
165  .chan = { { .pin = GPIO_PIN(PORT_B, 6), .cc_chan = 0 },
166  { .pin = GPIO_PIN(PORT_B, 7), .cc_chan = 1 } },
167  .af = GPIO_AF2,
168  .bus = APB1,
169  .irqn = TIM4_IRQn
170  },
171 };
172 
173 #define QDEC_0_ISR isr_tim3
174 #define QDEC_1_ISR isr_tim4
175 
176 #define QDEC_NUMOF ARRAY_SIZE(qdec_config)
183 static const spi_conf_t spi_config[] = {
184  {
185  .dev = SPI1,
186  .mosi_pin = GPIO_PIN(PORT_A, 7),
187  .miso_pin = GPIO_PIN(PORT_A, 6),
188  .sclk_pin = GPIO_PIN(PORT_A, 5),
189  .cs_pin = GPIO_PIN(PORT_A, 4),
190  .mosi_af = GPIO_AF5,
191  .miso_af = GPIO_AF5,
192  .sclk_af = GPIO_AF5,
193  .cs_af = GPIO_AF5,
194  .rccmask = RCC_APB2ENR_SPI1EN,
195  .apbbus = APB2,
196 #ifdef MODULE_PERIPH_DMA
197  .tx_dma = 0,
198  .tx_dma_chan = 3,
199  .rx_dma = 1,
200  .rx_dma_chan = 3,
201 #endif
202  },
203  {
204  .dev = SPI2,
205  .mosi_pin = GPIO_PIN(PORT_B, 15),
206  .miso_pin = GPIO_PIN(PORT_B, 14),
207  .sclk_pin = GPIO_PIN(PORT_B, 13),
208  .cs_pin = GPIO_PIN(PORT_B, 12),
209  .mosi_af = GPIO_AF5,
210  .miso_af = GPIO_AF5,
211  .sclk_af = GPIO_AF5,
212  .cs_af = GPIO_AF5,
213  .rccmask = RCC_APB1ENR_SPI2EN,
214  .apbbus = APB1,
215 #ifdef MODULE_PERIPH_DMA
216  .tx_dma = 2,
217  .tx_dma_chan = 0,
218  .rx_dma = 3,
219  .rx_dma_chan = 0,
220 #endif
221  },
222  {
223  .dev = SPI3,
224  .mosi_pin = GPIO_PIN(PORT_C, 12),
225  .miso_pin = GPIO_PIN(PORT_C, 11),
226  .sclk_pin = GPIO_PIN(PORT_C, 10),
227  .cs_pin = GPIO_UNDEF,
228  .mosi_af = GPIO_AF6,
229  .miso_af = GPIO_AF6,
230  .sclk_af = GPIO_AF6,
231  .cs_af = GPIO_AF6,
232  .rccmask = RCC_APB1ENR_SPI3EN,
233  .apbbus = APB1,
234 #ifdef MODULE_PERIPH_DMA
235  .tx_dma = 4,
236  .tx_dma_chan = 0,
237  .rx_dma = 5,
238  .rx_dma_chan = 0,
239 #endif
240  }
241 };
242 
243 #define SPI_NUMOF ARRAY_SIZE(spi_config)
256 static const adc_conf_t adc_config[] = {
257  {GPIO_PIN(PORT_A, 0), 0, 0},
258  {GPIO_PIN(PORT_A, 1), 0, 1},
259  {GPIO_PIN(PORT_A, 4), 0, 4},
260  {GPIO_PIN(PORT_B, 0), 0, 8},
261  {GPIO_PIN(PORT_C, 1), 0, 11},
262  {GPIO_PIN(PORT_C, 0), 0, 10},
263  {GPIO_UNDEF, 0, 18}, /* VBAT */
264 };
265 
266 #define VBAT_ADC ADC_LINE(6)
267 #define ADC_NUMOF ARRAY_SIZE(adc_config)
270 #ifdef __cplusplus
271 }
272 #endif
273 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:247
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:218
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF6
use alternate function 6
Definition: cpu_gpio.h:107
@ GPIO_AF3
use alternate function 3
Definition: cpu_gpio.h:104
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
PWM device configuration.
mini_timer_t * dev
Timer used.
Quadrature decoder configuration struct.
TIM_TypeDef * dev
Timer used.
Definition: cpu_qdec.h:49
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218