periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2017 Freie Universität Berlin
3  * SPDX-FileCopyrightText: 2017 Inria
4  * SPDX-License-Identifier: LGPL-2.1-only
5  */
6 
7 #pragma once
8 
20 /* Add specific clock configuration (HSE, LSE) for this board here */
21 #ifndef CONFIG_BOARD_HAS_LSE
22 #define CONFIG_BOARD_HAS_LSE 1
23 #endif
24 
25 #include "periph_cpu.h"
26 #include "clk_conf.h"
27 #include "cfg_rtt_default.h"
28 #include "cfg_timer_tim2.h"
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
38 static const uart_conf_t uart_config[] = {
39  {
40  .dev = USART2,
41  .rcc_mask = RCC_APB1ENR_USART2EN,
42  .rx_pin = GPIO_PIN(PORT_A, 3),
43  .tx_pin = GPIO_PIN(PORT_A, 2),
44  .rx_af = GPIO_AF4,
45  .tx_af = GPIO_AF4,
46  .bus = APB1,
47  .irqn = USART2_IRQn,
48  .type = STM32_USART,
49  .clk_src = 0, /* Use APB clock */
50  },
51  {
52  .dev = USART1,
53  .rcc_mask = RCC_APB2ENR_USART1EN,
54  .rx_pin = GPIO_PIN(PORT_A, 10),
55  .tx_pin = GPIO_PIN(PORT_A, 9),
56  .rx_af = GPIO_AF4,
57  .tx_af = GPIO_AF4,
58  .bus = APB2,
59  .irqn = USART1_IRQn,
60  .type = STM32_USART,
61  .clk_src = 0, /* Use APB clock */
62  },
63 #ifdef MODULE_PERIPH_LPUART
64  {
65  .dev = LPUART1,
66  .rcc_mask = RCC_APB1ENR_LPUART1EN,
67  .rx_pin = GPIO_PIN(PORT_C, 11),
68  .tx_pin = GPIO_PIN(PORT_C, 10),
69  .rx_af = GPIO_AF0,
70  .tx_af = GPIO_AF0,
71  .bus = APB1,
72  .irqn = LPUART1_IRQn,
73  .type = STM32_LPUART,
74  .clk_src = 0, /* Use APB clock */
75  },
76 #endif
77 };
78 
79 #define UART_0_ISR (isr_usart2)
80 #define UART_1_ISR (isr_usart1)
81 
82 #ifdef MODULE_PERIPH_LPUART
83 #define UART_2_ISR (isr_rng_lpuart1)
84 #endif
85 
86 #define UART_NUMOF ARRAY_SIZE(uart_config)
93 static const pwm_conf_t pwm_config[] = {
94  {
95  .dev = TIM3,
96  .rcc_mask = RCC_APB1ENR_TIM3EN,
97  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
98  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
99  { .pin = GPIO_PIN(PORT_C, 8) , .cc_chan = 2 },
100  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
101  .af = GPIO_AF2,
102  .bus = APB1
103  }
104 };
105 
106 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
113 static const spi_conf_t spi_config[] = {
114  {
115  .dev = SPI1,
116  .mosi_pin = GPIO_PIN(PORT_A, 7),
117  .miso_pin = GPIO_PIN(PORT_A, 6),
118  .sclk_pin = GPIO_PIN(PORT_A, 5),
119  .cs_pin = SPI_CS_UNDEF,
120  .mosi_af = GPIO_AF0,
121  .miso_af = GPIO_AF0,
122  .sclk_af = GPIO_AF0,
123  .cs_af = GPIO_AF0,
124  .rccmask = RCC_APB2ENR_SPI1EN,
125  .apbbus = APB2
126  }
127 };
128 
129 #define SPI_NUMOF ARRAY_SIZE(spi_config)
136 static const adc_conf_t adc_config[] = {
137  { GPIO_PIN(PORT_A, 0), 0 },
138  { GPIO_PIN(PORT_A, 1), 1 },
139  { GPIO_PIN(PORT_A, 4), 4 },
140  { GPIO_PIN(PORT_B, 0), 8 },
141  { GPIO_PIN(PORT_C, 1), 11 },
142  { GPIO_PIN(PORT_C, 0), 10 }
143 };
144 
145 #define ADC_NUMOF ARRAY_SIZE(adc_config)
152 static const i2c_conf_t i2c_config[] = {
153  {
154  .dev = I2C1,
155  .speed = I2C_SPEED_NORMAL,
156  .scl_pin = GPIO_PIN(PORT_B, 8),
157  .sda_pin = GPIO_PIN(PORT_B, 9),
158  .scl_af = GPIO_AF4,
159  .sda_af = GPIO_AF4,
160  .bus = APB1,
161  .rcc_mask = RCC_APB1ENR_I2C1EN,
162  .irqn = I2C1_IRQn
163  },
164  {
165  .dev = I2C2,
166  .speed = I2C_SPEED_NORMAL,
167  .scl_pin = GPIO_PIN(PORT_B, 13),
168  .sda_pin = GPIO_PIN(PORT_B, 14),
169  .scl_af = GPIO_AF5,
170  .sda_af = GPIO_AF5,
171  .bus = APB1,
172  .rcc_mask = RCC_APB1ENR_I2C2EN,
173  .irqn = I2C2_IRQn
174  }
175 };
176 
177 #define I2C_0_ISR isr_i2c1
178 #define I2C_1_ISR isr_i2c2
179 
180 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
183 #ifdef __cplusplus
184 }
185 #endif
186 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:65
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:247
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:218
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF0
use alternate function 0
Definition: cpu_gpio.h:101
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition: cpu_uart.h:38
@ STM32_USART
STM32 USART module type.
Definition: cpu_uart.h:37
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
ADC device configuration.
Definition: periph_cpu.h:377
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218