periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2016 Inria
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
21 /* This board provides an HSE */
22 #ifndef CONFIG_BOARD_HAS_HSE
23 #define CONFIG_BOARD_HAS_HSE 1
24 #endif
25 
26 #include "periph_cpu.h"
27 #include "clk_conf.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
37 static const timer_conf_t timer_config[] = {
38  {
39  .dev = TIM1,
40  .max = 0x0000ffff,
41  .rcc_mask = RCC_APB2ENR_TIM1EN,
42  .bus = APB2,
43  .irqn = TIM1_CC_IRQn
44  },
45  {
46  .dev = TIM3,
47  .max = 0x0000ffff,
48  .rcc_mask = RCC_APB1ENR_TIM3EN,
49  .bus = APB1,
50  .irqn = TIM3_IRQn
51  },
52 };
53 
54 #define TIMER_0_ISR (isr_tim1_cc)
55 #define TIMER_1_ISR (isr_tim3)
56 
57 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
64 static const uart_conf_t uart_config[] = {
65  {
66  .dev = USART1,
67  .rcc_mask = RCC_APB2ENR_USART1EN,
68  .rx_pin = GPIO_PIN(PORT_A, 10),
69  .tx_pin = GPIO_PIN(PORT_A, 9),
70  .rx_af = GPIO_AF1,
71  .tx_af = GPIO_AF1,
72  .bus = APB2,
73  .irqn = USART1_IRQn
74  }
75 };
76 
77 #define UART_0_ISR (isr_usart1)
78 
79 #define UART_NUMOF ARRAY_SIZE(uart_config)
86 static const pwm_conf_t pwm_config[] = {
87  {
88  .dev = TIM3,
89  .rcc_mask = RCC_APB1ENR_TIM3EN,
90  .chan = { { .pin = GPIO_PIN(PORT_A, 6), .cc_chan = 0},
91  { .pin = GPIO_PIN(PORT_A, 7), .cc_chan = 1},
92  { .pin = GPIO_UNDEF, .cc_chan = 0},
93  { .pin = GPIO_UNDEF, .cc_chan = 0} },
94  .af = GPIO_AF1,
95  .bus = APB1
96  }
97 };
98 
99 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
106 static const spi_conf_t spi_config[] = {
107  {
108  .dev = SPI1,
109  .mosi_pin = GPIO_PIN(PORT_A, 7),
110  .miso_pin = GPIO_PIN(PORT_A, 6),
111  .sclk_pin = GPIO_PIN(PORT_A, 5),
112  .cs_pin = GPIO_PIN(PORT_B, 1),
113  .mosi_af = GPIO_AF0,
114  .miso_af = GPIO_AF0,
115  .sclk_af = GPIO_AF0,
116  .cs_af = GPIO_AF0,
117  .rccmask = RCC_APB2ENR_SPI1EN,
118  .apbbus = APB2
119  },
120 };
121 
122 #define SPI_NUMOF ARRAY_SIZE(spi_config)
129 static const adc_conf_t adc_config[] = {
130  { GPIO_PIN(PORT_A, 0), 0 },
131  { GPIO_PIN(PORT_A, 1), 1 },
132  { GPIO_PIN(PORT_A, 2), 2 },
133  { GPIO_PIN(PORT_A, 3), 3 },
134  { GPIO_PIN(PORT_A, 4), 4 },
135  { GPIO_PIN(PORT_A, 5), 5 }
136 };
137 
138 #define ADC_NUMOF ARRAY_SIZE(adc_config)
141 #ifdef __cplusplus
142 }
143 #endif
144 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:36
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:247
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:218
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF0
use alternate function 0
Definition: cpu_gpio.h:101
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218