periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2014 Freie Universität Berlin
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
19 /* This board provides an HSE */
20 #ifndef CONFIG_BOARD_HAS_HSE
21 #define CONFIG_BOARD_HAS_HSE 1
22 #endif
23 
24 #include "periph_cpu.h"
25 #include "clk_conf.h"
26 #include "cfg_usb_otg_fs.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 static const dma_conf_t dma_config[] = {
37  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
38  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
39  { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */
40  { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */
41 };
42 
43 #define DMA_0_ISR isr_dma2_stream3
44 #define DMA_1_ISR isr_dma2_stream2
45 #define DMA_2_ISR isr_dma1_stream4
46 #define DMA_3_ISR isr_dma1_stream3
47 
48 #define DMA_NUMOF ARRAY_SIZE(dma_config)
55 static const timer_conf_t timer_config[] = {
56  {
57  .dev = TIM2,
58  .max = 0xffffffff,
59  .rcc_mask = RCC_APB1ENR_TIM2EN,
60  .bus = APB1,
61  .irqn = TIM2_IRQn
62  },
63  {
64  .dev = TIM5,
65  .max = 0xffffffff,
66  .rcc_mask = RCC_APB1ENR_TIM5EN,
67  .bus = APB1,
68  .irqn = TIM5_IRQn
69  }
70 };
71 
72 #define TIMER_0_ISR isr_tim2
73 #define TIMER_1_ISR isr_tim5
74 
75 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART2,
85  .rcc_mask = RCC_APB1ENR_USART2EN,
86  .rx_pin = GPIO_PIN(PORT_A, 3),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB1,
91  .irqn = USART2_IRQn,
92 #ifdef MODULE_PERIPH_DMA
93  .dma = DMA_STREAM_UNDEF,
94  .dma_chan = UINT8_MAX,
95 #endif
96  },
97  {
98  .dev = USART3,
99  .rcc_mask = RCC_APB1ENR_USART3EN,
100  .rx_pin = GPIO_PIN(PORT_D, 9),
101  .tx_pin = GPIO_PIN(PORT_D, 8),
102  .rx_af = GPIO_AF7,
103  .tx_af = GPIO_AF7,
104  .bus = APB1,
105  .irqn = USART3_IRQn,
106 #ifdef MODULE_PERIPH_DMA
107  .dma = DMA_STREAM_UNDEF,
108  .dma_chan = UINT8_MAX,
109 #endif
110  }
111 };
112 
113 #define UART_0_ISR (isr_usart2)
114 #define UART_1_ISR (isr_usart3)
115 
116 #define UART_NUMOF ARRAY_SIZE(uart_config)
126 static const adc_conf_t adc_config[] = {
127  {GPIO_PIN(PORT_A, 1), 0, 1},
128  {GPIO_PIN(PORT_A, 4), 0, 4},
129  {GPIO_PIN(PORT_C, 1), 1, 11},
130  {GPIO_PIN(PORT_C, 2), 1, 12},
131  {GPIO_UNDEF, 0, 18}, /* VBAT */
132 };
133 
134 #define VBAT_ADC ADC_LINE(4)
135 #define ADC_NUMOF ARRAY_SIZE(adc_config)
142 static const dac_conf_t dac_config[] = {
143  { .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
144  { .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
145 };
146 
147 #define DAC_NUMOF ARRAY_SIZE(dac_config)
154 static const pwm_conf_t pwm_config[] = {
155  {
156  .dev = TIM1,
157  .rcc_mask = RCC_APB2ENR_TIM1EN,
158  .chan = { { .pin = GPIO_PIN(PORT_E, 9), .cc_chan = 0 },
159  { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 1 },
160  { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 2 },
161  { .pin = GPIO_PIN(PORT_E, 14), .cc_chan = 3 } },
162  .af = GPIO_AF1,
163  .bus = APB2
164  },
165  {
166  .dev = TIM3,
167  .rcc_mask = RCC_APB1ENR_TIM3EN,
168  .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
169  { .pin = GPIO_PIN(PORT_B, 5), .cc_chan = 1 },
170  { .pin = GPIO_PIN(PORT_B, 0), .cc_chan = 2 },
171  { .pin = GPIO_PIN(PORT_B, 1), .cc_chan = 3 } },
172  .af = GPIO_AF2,
173  .bus = APB1
174  }
175 };
176 
177 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
184 static const spi_conf_t spi_config[] = {
185  {
186  .dev = SPI1,
187  .mosi_pin = GPIO_PIN(PORT_A, 7),
188  .miso_pin = GPIO_PIN(PORT_A, 6),
189  .sclk_pin = GPIO_PIN(PORT_A, 5),
190  .cs_pin = GPIO_PIN(PORT_A, 4),
191  .mosi_af = GPIO_AF5,
192  .miso_af = GPIO_AF5,
193  .sclk_af = GPIO_AF5,
194  .cs_af = GPIO_AF5,
195  .rccmask = RCC_APB2ENR_SPI1EN,
196  .apbbus = APB2,
197 #ifdef MODULE_PERIPH_DMA
198  .tx_dma = 0,
199  .tx_dma_chan = 3,
200  .rx_dma = 1,
201  .rx_dma_chan = 3,
202 #endif
203  },
204  {
205  .dev = SPI2,
206  .mosi_pin = GPIO_PIN(PORT_B, 15),
207  .miso_pin = GPIO_PIN(PORT_B, 14),
208  .sclk_pin = GPIO_PIN(PORT_B, 13),
209  .cs_pin = GPIO_PIN(PORT_B, 12),
210  .mosi_af = GPIO_AF5,
211  .miso_af = GPIO_AF5,
212  .sclk_af = GPIO_AF5,
213  .cs_af = GPIO_AF5,
214  .rccmask = RCC_APB1ENR_SPI2EN,
215  .apbbus = APB1,
216 #ifdef MODULE_PERIPH_DMA
217  .tx_dma = 2,
218  .tx_dma_chan = 0,
219  .rx_dma = 3,
220  .rx_dma_chan = 0,
221 #endif
222  },
223 };
224 
225 #define SPI_NUMOF ARRAY_SIZE(spi_config)
232 static const i2c_conf_t i2c_config[] = {
233  {
234  .dev = I2C1,
235  .speed = I2C_SPEED_NORMAL,
236  .scl_pin = GPIO_PIN(PORT_B, 6),
237  .sda_pin = GPIO_PIN(PORT_B, 9),
238  .scl_af = GPIO_AF4,
239  .sda_af = GPIO_AF4,
240  .bus = APB1,
241  .rcc_mask = RCC_APB1ENR_I2C1EN,
242  .clk = CLOCK_APB1,
243  .irqn = I2C1_EV_IRQn
244  }
245 };
246 
247 #define I2C_0_ISR isr_i2c1_ev
248 
249 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
252 #ifdef __cplusplus
253 }
254 #endif
255 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:65
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:36
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:247
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:218
static const dac_conf_t dac_config[]
DAC configuration.
Definition: periph_conf.h:249
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
#define CLOCK_APB1
Half AHB clock.
ADC device configuration.
Definition: periph_cpu.h:377
DAC line configuration data.
Definition: periph_cpu.h:300
gpio_t pin
pin connected to the line
Definition: periph_cpu.h:301
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218