periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2019 Inria
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
18 /* This board provides an LSE */
19 #ifndef CONFIG_BOARD_HAS_LSE
20 #define CONFIG_BOARD_HAS_LSE 1
21 #endif
22 
23 /* This board provides an HSE */
24 #ifndef CONFIG_BOARD_HAS_HSE
25 #define CONFIG_BOARD_HAS_HSE 1
26 #endif
27 
28 /* The HSE provides a 25MHz clock */
29 #ifndef CONFIG_CLOCK_HSE
30 #define CONFIG_CLOCK_HSE MHZ(25)
31 #endif
32 
33 #include "periph_cpu.h"
34 #include "clk_conf.h"
35 #include "cfg_rtt_default.h"
36 #if defined(MODULE_PERIPH_USBDEV_HS_UTMI)
38 #else
39 #include "cfg_usb_otg_fs.h"
40 #endif
41 #include "lcd_fmc.h"
42 
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46 
51 static const timer_conf_t timer_config[] = {
52  {
53  .dev = TIM2,
54  .max = 0xffffffff,
55  .rcc_mask = RCC_APB1ENR_TIM2EN,
56  .bus = APB1,
57  .irqn = TIM2_IRQn
58  }
59 };
60 
61 #define TIMER_0_ISR isr_tim2
62 
63 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
70 static const uart_conf_t uart_config[] = {
71  {
72  .dev = USART6,
73  .rcc_mask = RCC_APB2ENR_USART6EN,
74  .rx_pin = GPIO_PIN(PORT_C, 6),
75  .tx_pin = GPIO_PIN(PORT_C, 7),
76  .rx_af = GPIO_AF8,
77  .tx_af = GPIO_AF8,
78  .bus = APB2,
79  .irqn = USART6_IRQn,
80 #ifdef MODULE_PERIPH_UART_HW_FC
81  .cts_pin = GPIO_UNDEF,
82  .rts_pin = GPIO_UNDEF,
83  .cts_af = GPIO_AF8,
84  .rts_af = GPIO_AF8,
85 #endif
86  },
87  { /* Arduino connector (D0/D1) */
88  .dev = USART2,
89  .rcc_mask = RCC_APB1ENR_USART2EN,
90  .rx_pin = GPIO_PIN(PORT_A, 3),
91  .tx_pin = GPIO_PIN(PORT_A, 2),
92  .rx_af = GPIO_AF7,
93  .tx_af = GPIO_AF7,
94  .bus = APB1,
95  .irqn = USART2_IRQn,
96 #ifdef MODULE_PERIPH_UART_HW_FC
97  .cts_pin = GPIO_UNDEF,
98  .rts_pin = GPIO_UNDEF,
99  .cts_af = GPIO_AF8,
100  .rts_af = GPIO_AF8,
101 #endif
102  },
103  { /* PMOD connector */
104  .dev = UART7,
105  .rcc_mask = RCC_APB1ENR_UART7EN,
106  .rx_pin = GPIO_PIN(PORT_F, 6),
107  .tx_pin = GPIO_PIN(PORT_F, 7),
108  .rx_af = GPIO_AF8,
109  .tx_af = GPIO_AF8,
110  .bus = APB1,
111  .irqn = UART7_IRQn,
112 #ifdef MODULE_PERIPH_UART_HW_FC
113  .cts_pin = GPIO_PIN(PORT_F, 9),
114  .rts_pin = GPIO_PIN(PORT_F, 8),
115  .cts_af = GPIO_AF8,
116  .rts_af = GPIO_AF8,
117 #endif
118  },
119  { /* ESP-01 connector */
120  .dev = UART5,
121  .rcc_mask = RCC_APB1ENR_UART5EN,
122  .rx_pin = GPIO_PIN(PORT_D, 2),
123  .tx_pin = GPIO_PIN(PORT_C, 12),
124  .rx_af = GPIO_AF8,
125  .tx_af = GPIO_AF8,
126  .bus = APB1,
127  .irqn = UART5_IRQn,
128 #ifdef MODULE_PERIPH_UART_HW_FC
129  .cts_pin = GPIO_UNDEF,
130  .rts_pin = GPIO_UNDEF,
131  .cts_af = GPIO_AF8,
132  .rts_af = GPIO_AF8,
133 #endif
134  },
135 };
136 
137 #define UART_0_ISR (isr_usart6)
138 #define UART_1_ISR (isr_usart2)
139 #define UART_2_ISR (isr_uart4)
140 #define UART_3_ISR (isr_uart7)
141 #define UART_4_ISR (isr_uart5)
142 
143 #define UART_NUMOF ARRAY_SIZE(uart_config)
150 static const i2c_conf_t i2c_config[] = {
151  { /* Shared between Arduino D14/D15 and STMOD+ connector */
152  .dev = I2C2,
153  .speed = I2C_SPEED_NORMAL,
154  .scl_pin = GPIO_PIN(PORT_H, 4),
155  .sda_pin = GPIO_PIN(PORT_H, 5),
156  .scl_af = GPIO_AF4,
157  .sda_af = GPIO_AF4,
158  .bus = APB1,
159  .rcc_mask = RCC_APB1ENR_I2C2EN,
160  .rcc_sw_mask = RCC_DCKCFGR2_I2C2SEL_1,
161  .irqn = I2C2_ER_IRQn,
162  },
163  { /* Connected to touchscreen controller */
164  .dev = I2C3,
165  .speed = I2C_SPEED_NORMAL,
166  .scl_pin = GPIO_PIN(PORT_A, 8),
167  .sda_pin = GPIO_PIN(PORT_H, 8),
168  .scl_af = GPIO_AF4,
169  .sda_af = GPIO_AF4,
170  .bus = APB1,
171  .rcc_mask = RCC_APB1ENR_I2C3EN,
172  .rcc_sw_mask = RCC_DCKCFGR2_I2C3SEL_1,
173  .irqn = I2C3_ER_IRQn,
174  },
175  {
176  .dev = I2C1,
177  .speed = I2C_SPEED_NORMAL,
178  .scl_pin = GPIO_PIN(PORT_B, 8),
179  .sda_pin = GPIO_PIN(PORT_B, 9),
180  .scl_af = GPIO_AF4,
181  .sda_af = GPIO_AF4,
182  .bus = APB1,
183  .rcc_mask = RCC_APB1ENR_I2C1EN,
184  .rcc_sw_mask = RCC_DCKCFGR2_I2C1SEL_1,
185  .irqn = I2C1_ER_IRQn,
186  },
187 };
188 
189 #define I2C_0_ISR isr_i2c2_er
190 #define I2C_1_ISR isr_i2c3_er
191 #define I2C_2_ISR isr_i2c1_er
192 
193 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
200 static const spi_conf_t spi_config[] = {
201  { /* Arduino connector */
202  .dev = SPI1,
203  .mosi_pin = GPIO_PIN(PORT_B, 5),
204  .miso_pin = GPIO_PIN(PORT_B, 4),
205  .sclk_pin = GPIO_PIN(PORT_A, 5),
206  .cs_pin = SPI_CS_UNDEF,
207  .mosi_af = GPIO_AF5,
208  .miso_af = GPIO_AF5,
209  .sclk_af = GPIO_AF5,
210  .cs_af = GPIO_AF5,
211  .rccmask = RCC_APB2ENR_SPI1EN,
212  .apbbus = APB2
213  },
214  { /* PMOD connector */
215  .dev = SPI2,
216  .mosi_pin = GPIO_PIN(PORT_I, 3),
217  .miso_pin = GPIO_PIN(PORT_I, 2),
218  .sclk_pin = GPIO_PIN(PORT_I, 1),
219  .cs_pin = GPIO_PIN(PORT_I, 0),
220  .mosi_af = GPIO_AF5,
221  .miso_af = GPIO_AF5,
222  .sclk_af = GPIO_AF5,
223  .cs_af = GPIO_AF5,
224  .rccmask = RCC_APB1ENR_SPI2EN,
225  .apbbus = APB1
226  },
227 };
228 
229 #define SPI_NUMOF ARRAY_SIZE(spi_config)
240 static const fmc_conf_t fmc_config = {
241  .bus = AHB3,
242  .rcc_mask = RCC_AHB3ENR_FMCEN,
243 #if MODULE_PERIPH_FMC_NOR_SRAM
244  .ne1_pin = { .pin = GPIO_PIN(PORT_D, 7), .af = GPIO_AF12, }, /* PSRAM_NE1 signal, subbank 1 */
245  .ne2_pin = { .pin = GPIO_PIN(PORT_G, 9), .af = GPIO_AF12, }, /* LCD_NE signal, subbank 2 */
246  .noe_pin = { .pin = GPIO_PIN(PORT_D, 4), .af = GPIO_AF12, }, /* LCD_PSRAM_NOE */
247  .nwe_pin = { .pin = GPIO_PIN(PORT_D, 5), .af = GPIO_AF12, }, /* LCD_PSRAM_NWE signal */
248  .addr = {
249  { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* PSRAM_A0 / LCD_RS signal */
250  { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* PSRAM_A1 signal */
251  { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* PSRAM_A2 signal */
252  { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* PSRAM_A3 signal */
253  { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* PSRAM_A4 signal */
254  { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* PSRAM_A5 signal */
255  { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* PSRAM_A6 signal */
256  { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* PSRAM_A7 signal */
257  { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* PSRAM_A8 signal */
258  { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* PSRAM_A9 signal */
259  { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* PSRAM_A10 signal */
260  { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* PSRAM_A11 signal */
261  { .pin = GPIO_PIN(PORT_G, 2), .af = GPIO_AF12, }, /* PSRAM_A12 signal */
262  { .pin = GPIO_PIN(PORT_G, 3), .af = GPIO_AF12, }, /* PSRAM_A13 signal */
263  { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* PSRAM_A14 signal */
264  { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* PSRAM_A15 signal */
265  { .pin = GPIO_PIN(PORT_D, 11), .af = GPIO_AF12, }, /* PSRAM_A16 signal */
266  { .pin = GPIO_PIN(PORT_D, 12), .af = GPIO_AF12, }, /* PSRAM_A17 signal */
267  },
268 #endif
269  .data = {
270  { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* LCD_PSRAM_D0 signal */
271  { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* LCD_PSRAM_D1 signal */
272  { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* LCD_PSRAM_D2 signal */
273  { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* LCD_PSRAM_D3 signal */
274  { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* LCD_PSRAM_D4 signal */
275  { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* LCD_PSRAM_D5 signal */
276  { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* LCD_PSRAM_D6 signal */
277  { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* LCD_PSRAM_D7 signal */
278 #if MODULE_PERIPH_FMC_16BIT
279  { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* LCD_PSRAM_D8 signal */
280  { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* LCD_PSRAM_D9 signal */
281  { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* LCD_PSRAM_D10 signal */
282  { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* LCD_PSRAM_D11 signal */
283  { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* LCD_PSRAM_D12 signal */
284  { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* LCD_PSRAM_D13 signal */
285  { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* LCD_PSRAM_D14 signal */
286  { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* LCD_PSRAM_D15 signal */
287 #endif
288  },
289  .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* PSRAM_NBL0 signal (LB) */
290  .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* PSRAM_NBL1 signal (UB) */
291 };
292 
307  /* bank 1, subbank 1 is used for PSRAM with asynchronuous
308  * access in Mode 1, i.e. write timings are not used */
309  {
310  .bank = FMC_BANK_1,
311  .mem_type = FMC_SRAM,
312  .data_width = FMC_BUS_WIDTH_16BIT,
313  .address = 0x60000000, /* Bank 1, subbank 1 is mapped to 0x60000000 */
314  .size = KiB(512), /* Size in byte, 256K x 16 bit */
315  .nor_sram = {
316  .sub_bank = 1,
317  .ext_mode = false, /* Mode 1 used, no separate w_timing */
318  /* timings for IS66WV51216EBLL-55BLI
319  @216 MHz AHB clock */
320  .r_timing = { .addr_setup = 13, /* t_AA = max 60 ns (13 HCLKs a 4.63 ns) */
321  .data_setup = 6, /* t_SD = min 25 ns (6 HCLKs a 4.63 ns) */
322  .bus_turnaround = 3, }, /* 3 HCLKs a 4.63 ns */
323  },
324  },
325  /* bank 1, subbank 2 is used for LCD with asynchronuous
326  * access in Mode 1, i.e. write timings are not used */
327  {
328  .bank = FMC_BANK_1,
329  .mem_type = FMC_SRAM,
330  .data_width = FMC_BUS_WIDTH_16BIT,
331  .address = 0x64000000, /* Bank 1, subbank 2 is mapped to 0x64000000 */
332  .size = 4, /* 1 word for command @ 0x64000000 and
333  1 word for data @ 0x64000001 */
334  .nor_sram = {
335  .sub_bank = 2,
336  .ext_mode = false, /* Mode 1 used, no separate w_timing */
337  /* timing requirements for ST7789H2:
338  - t_AST min 0 ns (Address setup time)
339  - t_DST min 10 ns (Data setup time)
340  - t_WRL min 15 ns (WE LOW time)
341  - t_WRH min 15 ns (WE HIGH time)
342  - t_WRC min 66 ns (WE cycle time) */
343  .r_timing = { .addr_setup = 2, /* t_AST = 10 ns (2 HCLKs a 4.63 ns) */
344  .data_setup = 8, /* t_DST = 37 ns (8 HCLKs a 4.63 ns) */
345  .bus_turnaround = 5, }, /* t_WRH = 23 ns (5 HCLKs a 4.63 ns) */
346  },
347  },
348 };
349 
353 #define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
359 static const lcd_fmc_desc_t lcd_fmc_desc[] = {
360  {
361  .bank = FMC_BANK_CONFIG(1), /* second bank (fmc_bank_config[1]) is used */
362  .cmd_offset = 0x0, /* address 0x64000000 (offset 0x0) used for commands */
363  .data_offset = 0x2, /* address 0x64000002 (offset 0x2) used for commands */
364  }
365 };
366 
373 #define LCD_FMC_NUMOF 1
374 
375 #ifdef __cplusplus
376 }
377 #endif
378 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_G
port G
Definition: periph_cpu.h:52
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_F
port F
Definition: periph_cpu.h:51
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
@ PORT_H
port H
Definition: periph_cpu.h:51
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:65
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:36
static const lcd_fmc_desc_t lcd_fmc_desc[]
Descriptors of FMC banks used for LCDs.
Definition: periph_conf.h:359
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
Definition: periph_conf.h:306
static const fmc_conf_t fmc_config
FMC controller configuration.
Definition: periph_conf.h:240
Common configuration for STM32 OTG FS peripheral.
Common configuration for STM32 OTG HS peripheral with internal UTMI HS PHY.
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:110
@ GPIO_AF12
use alternate function 12
Definition: cpu_gpio.h:114
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
#define FMC_BANK_CONFIG(n)
Gives the configuration of n-th bank.
Definition: cpu_fmc.h:74
@ FMC_SRAM
SRAM.
Definition: cpu_fmc.h:340
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
Definition: cpu_fmc.h:352
@ FMC_BANK_1
Bank 1 is always available and used for NOR, PSRAM, SRAM.
Definition: cpu_fmc.h:320
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
Bank configuration structure.
Definition: cpu_fmc.h:359
fmc_bank_t bank
Bank1 .
Definition: cpu_fmc.h:360
FMC peripheral configuration.
Definition: cpu_fmc.h:277
uint8_t bus
AHB/APB bus.
Definition: cpu_fmc.h:278
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
Descriptor of the FMC bank used for a LCD.
Definition: lcd_fmc.h:48
const fmc_bank_conf_t * bank
FMC bank config used for the LCD.
Definition: lcd_fmc.h:49
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218
#define KiB(x)
A macro to return the bytes in x KiB.
Definition: units.h:28