cfg_usb_otg_fs_u5.h
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1 /*
2  * SPDX-FileCopyrightText: 2019 Koen Zandberg
3  * SPDX-FileCopyrightText: 2023 Gunar Schorcht
4  * SPDX-License-Identifier: LGPL-2.1-only
5  */
6 
7 #pragma once
8 
20 #include "periph_cpu.h"
21 #include "usbdev_synopsys_dwc2.h"
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
30 #define DWC2_USB_OTG_FS_ENABLED
31 
36  {
37  .periph = USB_OTG_FS_BASE,
38  .type = DWC2_USB_OTG_FS,
40  .rcc_mask = RCC_AHB2ENR1_OTGEN,
41  .irqn = OTG_FS_IRQn,
42  .ahb = AHB2,
43  .dm = GPIO_PIN(PORT_A, 11),
44  .dp = GPIO_PIN(PORT_A, 12),
45  .af = GPIO_AF10,
46  }
47 };
48 
52 #define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
53 
54 #ifdef __cplusplus
55 }
56 #endif
57 
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG FS configuration.
@ GPIO_AF10
use alternate function 10
Definition: cpu_gpio.h:112
USB OTG configuration.
uintptr_t periph
USB peripheral base address.
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_BUILTIN
on-chip FS PHY
@ DWC2_USB_OTG_FS
Full speed peripheral.