cfg_usb_otg_hs_phy_utmi.h

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/*
 * SPDX-FileCopyrightText: 2019 Koen Zandberg
 * SPDX-FileCopyrightText: 2022 Gunar Schorcht
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once
 
#include "periph_cpu.h"
#include "usbdev_synopsys_dwc2.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define DWC2_USB_OTG_HS_ENABLED
 
#ifndef USBPHYC_TUNE_VALUE
#define USBPHYC_TUNE_VALUE  0x00000f13U
#endif
 
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = {
    {
        .periph   = USB_OTG_HS_PERIPH_BASE,
        .type     = DWC2_USB_OTG_HS,
        .phy      = DWC2_USB_OTG_PHY_UTMI,
        .rcc_mask = RCC_AHB1ENR_OTGHSEN,
        .irqn     = OTG_HS_IRQn,
        .ahb      = AHB1,
        .dm       = GPIO_PIN(PORT_B, 14),
        .dp       = GPIO_PIN(PORT_B, 15),
        .af       = GPIO_AF10,
        .phy_tune = USBPHYC_TUNE_VALUE,
    }
};
 
#define USBDEV_NUMOF           ARRAY_SIZE(dwc2_usb_otg_fshs_config)
 
#ifdef __cplusplus
}
#endif