cfg_spi_default.h
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1 /*
2  * SPDX-FileCopyrightText: 2020 Koen Zandberg <koen@bergzand.net>
3  * SPDX-FileCopyrightText: 2023 Gunar Schorcht <gunar@schorcht.net>
4  * SPDX-License-Identifier: LGPL-2.1-only
5  */
6 
7 #pragma once
8 
20 #include "periph_cpu.h"
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
40 #ifndef SPI_DEV_1_USED
41 #define SPI_DEV_1_USED 0
42 #endif
43 
50 #ifndef SPI_DEV_0_CS
51 #define SPI_DEV_0_CS GPIO_PIN(PORT_B, 12)
52 #endif
53 
60 #ifndef SPI_DEV_1_CS
61 #define SPI_DEV_1_CS GPIO_PIN(PORT_B, 5)
62 #endif
63 
75 static const spi_conf_t spi_config[] = {
76  {
77  .dev = SPI1,
78  .mosi_pin = GPIO_PIN(PORT_B, 15),
79  .miso_pin = GPIO_PIN(PORT_B, 14),
80  .sclk_pin = GPIO_PIN(PORT_B, 13),
81  .cs_pin = SPI_DEV_0_CS,
82  .rcumask = RCU_APB1EN_SPI1EN_Msk,
83  .apbbus = APB1,
84  },
85 #if SPI_DEV_1_USED
86  {
87  .dev = SPI0,
88  .mosi_pin = GPIO_PIN(PORT_A, 7),
89  .miso_pin = GPIO_PIN(PORT_A, 6),
90  .sclk_pin = GPIO_PIN(PORT_A, 5),
91  .cs_pin = SPI_DEV_1_CS,
92  .rcumask = RCU_APB2EN_SPI0EN_Msk,
93  .apbbus = APB2,
94  },
95 #endif
96 };
97 
98 #define SPI_NUMOF ARRAY_SIZE(spi_config)
101 #ifdef __cplusplus
102 }
103 #endif
104 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define SPI_DEV_0_CS
Defines PB12 as the default CS signal for SPI_DEV(0)
#define SPI_DEV_1_CS
Defines PA4 as the default CS signal for SPI_DEV(1)
static const spi_conf_t spi_config[]
Default SPI device configuration.
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337