periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universität Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
21 /* HSE available on this board */
22 #ifndef CONFIG_BOARD_HAS_HSE
23 #define CONFIG_BOARD_HAS_HSE 1
24 #endif
25 
26 /* This board provides an LSE */
27 #ifndef CONFIG_BOARD_HAS_LSE
28 #define CONFIG_BOARD_HAS_LSE 1
29 #endif
30 
31 #include "periph_cpu.h"
32 #include "clk_conf.h"
33 #include "cfg_i2c1_pb8_pb9.h"
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
43 static const dma_conf_t dma_config[] = {
44  { .stream = 1 },
45  { .stream = 2 },
46 };
47 
48 #define DMA_SHARED_ISR_0 isr_dma1_ch2_3_dma2_ch1_2
49 #define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */
50 
51 #define DMA_NUMOF ARRAY_SIZE(dma_config)
58 static const timer_conf_t timer_config[] = {
59  {
60  .dev = TIM1,
61  .max = 0x0000ffff,
62  .rcc_mask = RCC_APB2ENR_TIM1EN,
63  .bus = APB2,
64  .irqn = TIM1_CC_IRQn
65  }
66 };
67 
68 #define TIMER_0_ISR isr_tim1_cc
69 
70 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
77 static const uart_conf_t uart_config[] = {
78  {
79  .dev = USART2,
80  .rcc_mask = RCC_APB1ENR_USART2EN,
81  .rx_pin = GPIO_PIN(PORT_A, 3),
82  .tx_pin = GPIO_PIN(PORT_A, 2),
83  .rx_af = GPIO_AF1,
84  .tx_af = GPIO_AF1,
85  .bus = APB1,
86  .irqn = USART2_IRQn,
87 #ifdef MODULE_PERIPH_DMA
88  .dma = 0,
89  .dma_chan = 0x9,
90 #endif
91  },
92  {
93  .dev = USART1,
94  .rcc_mask = RCC_APB2ENR_USART1EN,
95  .rx_pin = GPIO_PIN(PORT_A, 10),
96  .tx_pin = GPIO_PIN(PORT_A, 9),
97  .rx_af = GPIO_AF1,
98  .tx_af = GPIO_AF1,
99  .bus = APB2,
100  .irqn = USART1_IRQn,
101 #ifdef MODULE_PERIPH_DMA
102  .dma = 0,
103  .dma_chan = 0x8,
104 #endif
105  },
106  {
107  .dev = USART3,
108  .rcc_mask = RCC_APB1ENR_USART3EN,
109  .rx_pin = GPIO_PIN(PORT_C, 11),
110  .tx_pin = GPIO_PIN(PORT_C, 10),
111  .rx_af = GPIO_AF1,
112  .tx_af = GPIO_AF1,
113  .bus = APB1,
114  .irqn = USART3_8_IRQn,
115 #ifdef MODULE_PERIPH_DMA
116  .dma = 0,
117  .dma_chan = 0xA,
118 #endif
119  },
120 };
121 
122 #define UART_0_ISR (isr_usart2)
123 #define UART_1_ISR (isr_usart1)
124 #define UART_2_ISR (isr_usart3_8)
125 
126 #define UART_NUMOF ARRAY_SIZE(uart_config)
133 static const spi_conf_t spi_config[] = {
134  {
135  .dev = SPI1,
136  .mosi_pin = GPIO_PIN(PORT_A, 7),
137  .miso_pin = GPIO_PIN(PORT_A, 6),
138  .sclk_pin = GPIO_PIN(PORT_A, 5),
139  .cs_pin = GPIO_PIN(PORT_B, 6),
140  .mosi_af = GPIO_AF0,
141  .miso_af = GPIO_AF0,
142  .sclk_af = GPIO_AF0,
143  .cs_af = GPIO_AF0,
144  .rccmask = RCC_APB2ENR_SPI1EN,
145  .apbbus = APB2,
146 #ifdef MODULE_PERIPH_DMA
147  .tx_dma = 1,
148  .tx_dma_chan = 0,
149  .rx_dma = 0,
150  .rx_dma_chan = 0,
151 #endif
152  }
153 };
154 
155 #define SPI_NUMOF ARRAY_SIZE(spi_config)
162 static const pwm_conf_t pwm_config[] = {
163  {
164  .dev = TIM2,
165  .rcc_mask = RCC_APB1ENR_TIM2EN,
166  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
167  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
168  { .pin = GPIO_PIN(PORT_B, 11) , .cc_chan = 3 },
169  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
170  .af = GPIO_AF2,
171  .bus = APB1
172  },
173  {
174  .dev = TIM3,
175  .rcc_mask = RCC_APB1ENR_TIM3EN,
176  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
177  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
178  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
179  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
180  .af = GPIO_AF0,
181  .bus = APB1
182  }
183 };
184 
185 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
192 static const adc_conf_t adc_config[] = {
193  { GPIO_PIN(PORT_A, 0), 0 },
194  { GPIO_PIN(PORT_A, 1), 1 },
195  { GPIO_PIN(PORT_A, 4), 4 },
196  { GPIO_PIN(PORT_B, 0), 8 },
197  { GPIO_PIN(PORT_C, 1), 11 },
198  { GPIO_PIN(PORT_C, 0), 10 },
199  { GPIO_UNDEF, 18 }, /* VBAT */
200 };
201 
202 #define VBAT_ADC ADC_LINE(6)
203 #define ADC_NUMOF ARRAY_SIZE(adc_config)
206 #ifdef __cplusplus
207 }
208 #endif
209 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
Common configuration for STM32 I2C.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF0
use alternate function 0
Definition: cpu_gpio.h:101
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218