periph_conf.h
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1 /*
2  * Copyright (C) 2016-2017 OTA keys S.A.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
23 /* This board provides an LSE */
24 #ifndef CONFIG_BOARD_HAS_LSE
25 #define CONFIG_BOARD_HAS_LSE 1
26 #endif
27 
28 /* This board provides an HSE */
29 #ifndef CONFIG_BOARD_HAS_HSE
30 #define CONFIG_BOARD_HAS_HSE 1
31 #endif
32 
33 #include "periph_cpu.h"
34 #include "clk_conf.h"
35 #include "cfg_i2c1_pb8_pb9.h"
36 #include "cfg_usb_otg_fs.h"
37 #include "mii.h"
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
47 static const dma_conf_t dma_config[] = {
48  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
49  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
50  { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX/USART3_TX */
51  { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */
52  { .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */
53  { .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
54  { .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */
55 };
56 
57 #define DMA_0_ISR isr_dma2_stream2
58 #define DMA_1_ISR isr_dma2_stream3
59 #define DMA_2_ISR isr_dma1_stream3
60 #define DMA_3_ISR isr_dma1_stream4
61 #define DMA_4_ISR isr_dma2_stream6
62 #define DMA_5_ISR isr_dma1_stream6
63 #define DMA_6_ISR isr_dma2_stream0
64 
65 #define DMA_NUMOF ARRAY_SIZE(dma_config)
72 static const pwm_conf_t pwm_config[] = {
73  {
74  .dev = TIM1,
75  .rcc_mask = RCC_APB2ENR_TIM1EN,
76  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
77  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
78  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
79  { .pin = GPIO_UNDEF, .cc_chan = 0} },
80  .af = GPIO_AF1,
81  .bus = APB2
82  },
83  {
84  .dev = TIM4,
85  .rcc_mask = RCC_APB1ENR_TIM4EN,
86  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
87  { .pin = GPIO_UNDEF, .cc_chan = 0},
88  { .pin = GPIO_UNDEF, .cc_chan = 0},
89  { .pin = GPIO_UNDEF, .cc_chan = 0} },
90  .af = GPIO_AF2,
91  .bus = APB1
92  },
93 };
94 
95 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
102 static const timer_conf_t timer_config[] = {
103  {
104  .dev = TIM2,
105  .max = 0xffffffff,
106  .rcc_mask = RCC_APB1ENR_TIM2EN,
107  .bus = APB1,
108  .irqn = TIM2_IRQn
109  },
110  {
111  .dev = TIM5,
112  .max = 0xffffffff,
113  .rcc_mask = RCC_APB1ENR_TIM5EN,
114  .bus = APB1,
115  .irqn = TIM5_IRQn
116  }
117 };
118 
119 #define TIMER_0_ISR isr_tim2
120 #define TIMER_1_ISR isr_tim5
121 
122 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
129 static const uart_conf_t uart_config[] = {
130  {
131  .dev = USART3,
132  .rcc_mask = RCC_APB1ENR_USART3EN,
133  .rx_pin = GPIO_PIN(PORT_D, 9),
134  .tx_pin = GPIO_PIN(PORT_D, 8),
135  .rx_af = GPIO_AF7,
136  .tx_af = GPIO_AF7,
137  .bus = APB1,
138  .irqn = USART3_IRQn,
139 #ifdef MODULE_PERIPH_DMA
140  .dma = 2,
141  .dma_chan = 4
142 #endif
143  },
144  {
145  .dev = USART6,
146  .rcc_mask = RCC_APB2ENR_USART6EN,
147  .rx_pin = GPIO_PIN(PORT_G, 9),
148  .tx_pin = GPIO_PIN(PORT_G, 14),
149  .rx_af = GPIO_AF8,
150  .tx_af = GPIO_AF8,
151  .bus = APB2,
152  .irqn = USART6_IRQn,
153 #ifdef MODULE_PERIPH_DMA
154  .dma = 4,
155  .dma_chan = 5
156 #endif
157  },
158  {
159  .dev = USART2,
160  .rcc_mask = RCC_APB1ENR_USART2EN,
161  .rx_pin = GPIO_PIN(PORT_D, 6),
162  .tx_pin = GPIO_PIN(PORT_D, 5),
163  .rx_af = GPIO_AF7,
164  .tx_af = GPIO_AF7,
165  .bus = APB1,
166  .irqn = USART2_IRQn,
167 #ifdef MODULE_PERIPH_DMA
168  .dma = 5,
169  .dma_chan = 4
170 #endif
171  },
172 };
173 
174 #define UART_0_ISR (isr_usart3)
175 #define UART_1_ISR (isr_usart6)
176 #define UART_2_ISR (isr_usart2)
177 
178 #define UART_NUMOF ARRAY_SIZE(uart_config)
185 static const spi_conf_t spi_config[] = {
186  {
187  .dev = SPI1,
188  .mosi_pin = GPIO_PIN(PORT_A, 7),
189  .miso_pin = GPIO_PIN(PORT_A, 6),
190  .sclk_pin = GPIO_PIN(PORT_A, 5),
191  .cs_pin = GPIO_PIN(PORT_A, 4),
192  .mosi_af = GPIO_AF5,
193  .miso_af = GPIO_AF5,
194  .sclk_af = GPIO_AF5,
195  .cs_af = GPIO_AF5,
196  .rccmask = RCC_APB2ENR_SPI1EN,
197  .apbbus = APB2,
198 #ifdef MODULE_PERIPH_DMA
199  .tx_dma = 1,
200  .tx_dma_chan = 3,
201  .rx_dma = 0,
202  .rx_dma_chan = 3,
203 #endif
204  },
205  {
206  .dev = SPI2,
207  .mosi_pin = GPIO_PIN(PORT_B, 15),
208  .miso_pin = GPIO_PIN(PORT_C, 2),
209  .sclk_pin = GPIO_PIN(PORT_B, 13),
210  .cs_pin = GPIO_PIN(PORT_B, 12),
211  .mosi_af = GPIO_AF5,
212  .miso_af = GPIO_AF5,
213  .sclk_af = GPIO_AF5,
214  .cs_af = GPIO_AF5,
215  .rccmask = RCC_APB1ENR_SPI2EN,
216  .apbbus = APB1,
217 #ifdef MODULE_PERIPH_DMA
218  .tx_dma = 3,
219  .tx_dma_chan = 0,
220  .rx_dma = 2,
221  .rx_dma_chan = 0,
222 #endif
223  }
224 };
225 
226 #define SPI_NUMOF ARRAY_SIZE(spi_config)
250 static const adc_conf_t adc_config[] = {
251  { .pin = GPIO_PIN(PORT_A, 3), .dev = 0, .chan = 3 }, /* ADC123_IN3 */
252  { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 10 }, /* ADC123_IN10 */
253  { .pin = GPIO_PIN(PORT_C, 3), .dev = 0, .chan = 13 }, /* ADC123_IN13 */
254  { .pin = GPIO_PIN(PORT_F, 3), .dev = 2, .chan = 9 }, /* ADC3_IN9 */
255  { .pin = GPIO_PIN(PORT_F, 5), .dev = 2, .chan = 15 }, /* ADC3_IN15 */
256  { .pin = GPIO_PIN(PORT_F, 10), .dev = 2, .chan = 8 }, /* ADC3_IN8 */
257  { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 }, /* VBAT */
258 };
259 
263 #define VBAT_ADC ADC_LINE(6)
264 
268 #define ADC_NUMOF ARRAY_SIZE(adc_config)
269 
276 static const eth_conf_t eth_config = {
277  .mode = RMII,
279  .dma = 6,
280  .dma_chan = 8,
281  .phy_addr = 0x00,
282  .pins = {
283  GPIO_PIN(PORT_G, 13),
284  GPIO_PIN(PORT_B, 13),
285  GPIO_PIN(PORT_G, 11),
286  GPIO_PIN(PORT_C, 4),
287  GPIO_PIN(PORT_C, 5),
288  GPIO_PIN(PORT_A, 7),
289  GPIO_PIN(PORT_C, 1),
290  GPIO_PIN(PORT_A, 2),
291  GPIO_PIN(PORT_A, 1),
292  }
293 };
294 
295 #define ETH_DMA_ISR isr_dma2_stream0
296 
299 #ifdef __cplusplus
300 }
301 #endif
302 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_G
port G
Definition: periph_cpu.h:52
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_F
port F
Definition: periph_cpu.h:51
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
Common configuration for STM32 I2C.
Common configuration for STM32 OTG FS peripheral.
@ RMII
Configuration for RMII.
Definition: cpu_eth.h:36
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
#define MII_BMCR_FULL_DPLX
Set for full duplex.
Definition: mii.h:68
#define MII_BMCR_SPEED_100
Set speed to 100 Mbps.
Definition: mii.h:72
Interface definition for MII/RMII h.
ADC device configuration.
Definition: periph_cpu.h:377
gpio_t pin
pin connected to the channel
Definition: periph_cpu.h:287
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
Ethernet Peripheral configuration.
Definition: cpu_eth.h:43
eth_mode_t mode
Select configuration mode.
Definition: cpu_eth.h:44
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218