periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * Copyright (C) 2015 Freie Universität Berlin
4  * Copyright (C) 2015 Hamburg University of Applied Sciences
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
11 #pragma once
12 
25 /* This board provides an LSE */
26 #ifndef CONFIG_BOARD_HAS_LSE
27 #define CONFIG_BOARD_HAS_LSE 1
28 #endif
29 
30 /* This board provides an HSE */
31 #ifndef CONFIG_BOARD_HAS_HSE
32 #define CONFIG_BOARD_HAS_HSE 1
33 #endif
34 
35 #include "periph_cpu.h"
36 #include "clk_conf.h"
37 #include "cfg_timer_tim2.h"
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
53 static const adc_conf_t adc_config[] = {
54  { .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 1 }, /* ADC_IN1, fast */
55  { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 2 }, /* ADC_IN2, fast */
56  { .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 5 }, /* ADC_IN5, fast */
57  { .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 11 }, /* ADC_IN11, slow */
58  { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 7 }, /* ADC_IN7, slow */
59  { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 6 }, /* ADC_IN6, slow */
60  { .pin = GPIO_UNDEF, .dev = 0, .chan = 17 }, /* VBAT */
61 };
62 
63 #define VBAT_ADC ADC_LINE(6)
64 #define ADC_NUMOF ARRAY_SIZE(adc_config)
71 static const uart_conf_t uart_config[] = {
72  {
73  .dev = USART2,
74  .rcc_mask = RCC_APB1ENR_USART2EN,
75  .rx_pin = GPIO_PIN(PORT_A, 3),
76  .tx_pin = GPIO_PIN(PORT_A, 2),
77  .rx_af = GPIO_AF7,
78  .tx_af = GPIO_AF7,
79  .bus = APB1,
80  .irqn = USART2_IRQn
81  },
82  {
83  .dev = USART1,
84  .rcc_mask = RCC_APB2ENR_USART1EN,
85  .rx_pin = GPIO_PIN(PORT_A, 10),
86  .tx_pin = GPIO_PIN(PORT_A, 9),
87  .rx_af = GPIO_AF7,
88  .tx_af = GPIO_AF7,
89  .bus = APB2,
90  .irqn = USART1_IRQn
91  },
92  {
93  .dev = USART3,
94  .rcc_mask = RCC_APB1ENR_USART3EN,
95  .rx_pin = GPIO_PIN(PORT_C, 11),
96  .tx_pin = GPIO_PIN(PORT_C, 10),
97  .rx_af = GPIO_AF7,
98  .tx_af = GPIO_AF7,
99  .bus = APB1,
100  .irqn = USART3_IRQn
101  }
102 };
103 
104 #define UART_0_ISR (isr_usart2)
105 #define UART_1_ISR (isr_usart1)
106 #define UART_2_ISR (isr_usart3)
107 
108 #define UART_NUMOF ARRAY_SIZE(uart_config)
115 static const pwm_conf_t pwm_config[] = {
116  {
117  .dev = TIM16,
118  .rcc_mask = RCC_APB2ENR_TIM16EN,
119  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
120  { .pin = GPIO_UNDEF, .cc_chan = 0 },
121  { .pin = GPIO_UNDEF, .cc_chan = 0 },
122  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
123  .af = GPIO_AF1,
124  .bus = APB2
125  }
126 };
127 
128 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
135 static const spi_conf_t spi_config[] = {
136  {
137  .dev = SPI2,
138  .mosi_pin = GPIO_PIN(PORT_B, 15),
139  .miso_pin = GPIO_PIN(PORT_B, 14),
140  .sclk_pin = GPIO_PIN(PORT_B, 13),
141  .cs_pin = GPIO_PIN(PORT_B, 12),
142  .mosi_af = GPIO_AF5,
143  .miso_af = GPIO_AF5,
144  .sclk_af = GPIO_AF5,
145  .cs_af = GPIO_AF5,
146  .rccmask = RCC_APB1ENR_SPI2EN,
147  .apbbus = APB1
148  }
149 };
150 
151 #define SPI_NUMOF ARRAY_SIZE(spi_config)
158 static const i2c_conf_t i2c_config[] = {
159  {
160  .dev = I2C1,
161  .speed = I2C_SPEED_NORMAL,
162  .scl_pin = GPIO_PIN(PORT_B, 8),
163  .sda_pin = GPIO_PIN(PORT_B, 9),
164  .scl_af = GPIO_AF4,
165  .sda_af = GPIO_AF4,
166  .bus = APB1,
167  .rcc_mask = RCC_APB1ENR_I2C1EN,
168  .rcc_sw_mask = RCC_CFGR3_I2C1SW,
169  .irqn = I2C1_ER_IRQn
170  },
171  {
172  .dev = I2C3,
173  .speed = I2C_SPEED_NORMAL,
174  .scl_pin = GPIO_PIN(PORT_A, 8),
175  .sda_pin = GPIO_PIN(PORT_A, 5),
176  .scl_af = GPIO_AF5,
177  .sda_af = GPIO_AF8,
178  .bus = APB1,
179  .rcc_mask = RCC_APB1ENR_I2C3EN,
180  .rcc_sw_mask = RCC_CFGR3_I2C3SW,
181  .irqn = I2C3_ER_IRQn
182  }
183 };
184 
185 #define I2C_0_ISR isr_i2c1_er
186 #define I2C_1_ISR isr_i2c3_er
187 
188 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
191 #ifdef __cplusplus
192 }
193 #endif
194 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
ADC device configuration.
Definition: periph_cpu.h:377
gpio_t pin
pin connected to the channel
Definition: periph_cpu.h:287
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218