periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
21 /* This board provides an LSE */
22 #ifndef CONFIG_BOARD_HAS_LSE
23 #define CONFIG_BOARD_HAS_LSE 1
24 #endif
25 
26 /* This board provides an HSE */
27 #ifndef CONFIG_BOARD_HAS_HSE
28 #define CONFIG_BOARD_HAS_HSE 1
29 #endif
30 
31 #include "periph_cpu.h"
32 #include "clk_conf.h"
33 #include "cfg_i2c1_pb8_pb9.h"
34 #include "cfg_timer_tim5.h"
35 #include "cfg_usb_otg_fs.h"
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
45 static const dma_conf_t dma_config[] = {
46  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
47  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
48 };
49 
50 #define DMA_0_ISR isr_dma2_stream3
51 #define DMA_1_ISR isr_dma2_stream2
52 
53 #define DMA_NUMOF ARRAY_SIZE(dma_config)
60 static const uart_conf_t uart_config[] = {
61  {
62  .dev = USART3,
63  .rcc_mask = RCC_APB1ENR_USART3EN,
64  .rx_pin = GPIO_PIN(PORT_D, 9),
65  .tx_pin = GPIO_PIN(PORT_D, 8),
66  .rx_af = GPIO_AF7,
67  .tx_af = GPIO_AF7,
68  .bus = APB1,
69  .irqn = USART3_IRQn,
70 #ifdef MODULE_PERIPH_DMA
71  .dma = DMA_STREAM_UNDEF,
72  .dma_chan = UINT8_MAX,
73 #endif
74  },
75  {
76  .dev = USART6,
77  .rcc_mask = RCC_APB2ENR_USART6EN,
78  .rx_pin = GPIO_PIN(PORT_G, 9),
79  .tx_pin = GPIO_PIN(PORT_G, 14),
80  .rx_af = GPIO_AF8,
81  .tx_af = GPIO_AF8,
82  .bus = APB2,
83  .irqn = USART6_IRQn,
84 #ifdef MODULE_PERIPH_DMA
85  .dma = DMA_STREAM_UNDEF,
86  .dma_chan = UINT8_MAX,
87 #endif
88  },
89  {
90  .dev = USART2,
91  .rcc_mask = RCC_APB1ENR_USART2EN,
92  .rx_pin = GPIO_PIN(PORT_D, 6),
93  .tx_pin = GPIO_PIN(PORT_D, 5),
94  .rx_af = GPIO_AF7,
95  .tx_af = GPIO_AF7,
96  .bus = APB1,
97  .irqn = USART2_IRQn,
98 #ifdef MODULE_PERIPH_DMA
99  .dma = DMA_STREAM_UNDEF,
100  .dma_chan = UINT8_MAX,
101 #endif
102  },
103 };
104 
105 #define UART_0_ISR (isr_usart3)
106 #define UART_1_ISR (isr_usart6)
107 #define UART_2_ISR (isr_usart2)
108 
109 #define UART_NUMOF ARRAY_SIZE(uart_config)
116 static const pwm_conf_t pwm_config[] = {
117  {
118  .dev = TIM1,
119  .rcc_mask = RCC_APB2ENR_TIM1EN,
120  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
121  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
122  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
123  { .pin = GPIO_UNDEF, .cc_chan = 0} },
124  .af = GPIO_AF1,
125  .bus = APB2
126  },
127  {
128  .dev = TIM4,
129  .rcc_mask = RCC_APB1ENR_TIM4EN,
130  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
131  { .pin = GPIO_UNDEF, .cc_chan = 0},
132  { .pin = GPIO_UNDEF, .cc_chan = 0},
133  { .pin = GPIO_UNDEF, .cc_chan = 0} },
134  .af = GPIO_AF2,
135  .bus = APB1
136  },
137 };
138 
139 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
146 static const spi_conf_t spi_config[] = {
147  {
148  .dev = SPI1,
149  .mosi_pin = GPIO_PIN(PORT_A, 7),
150  .miso_pin = GPIO_PIN(PORT_A, 6),
151  .sclk_pin = GPIO_PIN(PORT_A, 5),
152  .cs_pin = SPI_CS_UNDEF,
153  .mosi_af = GPIO_AF5,
154  .miso_af = GPIO_AF5,
155  .sclk_af = GPIO_AF5,
156  .cs_af = GPIO_AF5,
157  .rccmask = RCC_APB2ENR_SPI1EN,
158  .apbbus = APB2,
159 #ifdef MODULE_PERIPH_DMA
160  .tx_dma = 0,
161  .tx_dma_chan = 3,
162  .rx_dma = 1,
163  .rx_dma_chan = 3,
164 #endif
165  },
166 };
167 
168 #define SPI_NUMOF ARRAY_SIZE(spi_config)
192 static const adc_conf_t adc_config[] = {
193  { .pin = GPIO_PIN(PORT_A, 0), .dev = 2, .chan = 3 }, /* ADC123_IN3 */
194  { .pin = GPIO_PIN(PORT_A, 1), .dev = 2, .chan = 10 }, /* ADC123_IN10 */
195  { .pin = GPIO_PIN(PORT_A, 4), .dev = 2, .chan = 13 }, /* ADC123_IN13 */
196  { .pin = GPIO_PIN(PORT_B, 0), .dev = 2, .chan = 9 }, /* ADC123_IN9 */
197  { .pin = GPIO_PIN(PORT_C, 1), .dev = 2, .chan = 15 }, /* ADC3_IN15 */
198  { .pin = GPIO_PIN(PORT_C, 0), .dev = 2, .chan = 8 }, /* ADC3_IN8 */
199  { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 }, /* VBAT */
200 };
201 
205 #define ADC_NUMOF ARRAY_SIZE(adc_config)
206 
207 #define VBAT_ADC ADC_LINE(6)
211 #ifdef __cplusplus
212 }
213 #endif
214 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_G
port G
Definition: periph_cpu.h:52
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:192
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
gpio_t pin
pin connected to the channel
Definition: periph_cpu.h:287
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218