cc26x2_cc13x2_prcm.h

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/*
 * Copyright (C) 2016 Leon George
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#pragma once
 
#include <cc26xx_cc13xx.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef struct {
    reg32_t CTL0; 
    reg32_t CTL1; 
    reg32_t RADCEXTCFG; 
    reg32_t AMPCOMPCTL; 
    reg32_t AMPCOMPTH1; 
    reg32_t AMPCOMPTH2; 
    reg32_t ANABYPASSVAL1; 
    reg32_t ANABYPASSVAL2; 
    reg32_t ATESTCTL; 
    reg32_t ADCDOUBLERNANOAMPCTL; 
    reg32_t XOSCHFCTL; 
    reg32_t LFOSCCTL; 
    reg32_t RCOSCHFCTL; 
    reg32_t RCOSCMFCTL; 
    reg32_t __reserved1; 
    reg32_t STAT0; 
    reg32_t STAT1; 
    reg32_t STAT2; 
} ddi0_osc_regs_t;
 
typedef struct {
    reg32_m16_t CTL0; 
    reg32_m16_t CTL1; 
    reg32_m16_t RADCEXTCFG; 
    reg32_m16_t AMPCOMPCTL; 
    reg32_m16_t AMPCOMPTH1; 
    reg32_m16_t AMPCOMPTH2; 
    reg32_m16_t ANABYPASSVAL1; 
    reg32_m16_t ANABYPASSVAL2; 
    reg32_m16_t ATESTCTL; 
    reg32_m16_t ADCDOUBLERNANOAMPCTL; 
    reg32_m16_t XOSCHFCTL; 
    reg32_m16_t LFOSCCTL; 
    reg32_m16_t RCOSCHFCTL; 
    reg32_m16_t RCOSCMFCTL; 
    reg32_m16_t __reserved1; 
    reg32_m16_t STAT0; 
    reg32_m16_t STAT1; 
    reg32_m16_t STAT2; 
} ddi0_osc_regs_m16_t;
 
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_m        0x00000001
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_s        0
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC     0x00000001
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC    0x00000000
#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_m        0x0000000C
#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_s        2
#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL         0x00000180
#define DDI_0_OSC_CTL0_CLK_LOSS_EN              0x00000200
#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS       0x00000400
#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE       0x00000800
#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED         0x00001000
#define DDI_0_OSC_CTL0_HPOSC_MODE_EN            0x00004000
#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_m       0x01000000
#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION   0x02000000
#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION   0x0C000000
#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000
#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL  0x20000000
#define DDI_0_OSC_CTL0_XTAL_IS_24M              0x80000000
#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING  0x00000001
#define DDI_0_OSC_STAT0_SCLK_HF_SRC_m           0x10000000
#define DDI_0_OSC_STAT0_SCLK_HF_SRC_s           28
#define DDI_0_OSC_STAT0_SCLK_LF_SRC_m           0x60000000
#define DDI_0_OSC_STAT0_SCLK_LF_SRC_s           29
#define DDI_DIR              0x00000000
#define DDI_SET              0x00000080
#define DDI_CLR              0x00000100
#define DDI_MASK4B           0x00000200
#define DDI_MASK8B           0x00000300
#define DDI_MASK16B          0x00000400
#define DDI0_OSC_BASE        (PERIPH_BASE + 0xCA000)
#define DDI0_OSC_BASE_M16    (DDI0_OSC_BASE + DDI_MASK16B)
#define DDI_0_OSC            ((ddi0_osc_regs_t *) (DDI0_OSC_BASE))
#define DDI_0_OSC_M16        ((ddi0_osc_regs_m16_t *) (DDI0_OSC_BASE_M16))
 
#define OSC_RCOSC_HF         0x00000000 
#define OSC_XOSC_HF          0x00000001 
void osc_hf_source_switch(uint32_t osc);
typedef struct {
   reg32_t __reserved1; 
   reg32_t AUXSCECLK; 
   reg32_t RAMCFG; 
   reg32_t __reserved2; 
   reg32_t PWRCTL; 
   reg32_t PWRSTAT; 
   reg32_t SHUTDOWN; 
   reg32_t RECHARGECFG; 
   reg32_t RECHARGESTAT; 
   reg32_t OSCCFG; 
   reg32_t RESETCTL; 
   reg32_t SLEEPCTL; 
   reg32_t __reserved3; 
   reg32_t JTAGCFG; 
   reg32_t __reserved4; 
   reg32_t JTAGUSERCODE; 
} aon_pmctl_regs_t;
 
#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001
#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_m 0x02000000
#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_m 0x01000000
#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_m 0x00020000
#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_m 0x00010000
#define AON_PMCTL_RESETCTL_BOOT_DET_1_m     0x00002000
#define AON_PMCTL_RESETCTL_BOOT_DET_0_m     0x00001000
#define AON_PMCTL_RESETCTL_BOOT_DET_0_s     12
#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_m 0x00000010
#define AON_PMCTL_BASE       (PERIPH_BASE + 0x90000)
#define AON_PMCTL            ((aon_pmctl_regs_t *) (AON_PMCTL_BASE))
 
typedef struct {
    reg32_t CTL; 
    reg32_t EVFLAGS; 
    reg32_t SEC; 
    reg32_t SUBSEC; 
    reg32_t SUBSECINC; 
    reg32_t CHCTL; 
    reg32_t CH0CMP; 
    reg32_t CH1CMP; 
    reg32_t CH2CMP; 
    reg32_t CH2CMPINC; 
    reg32_t CH1CAPT; 
    reg32_t SYNC; 
    reg32_t TIME; 
    reg32_t SYNCLF; 
} aon_rtc_regs_t;
 
#define AON_RTC_CTL_RTC_UPD_EN 0x00000002
 
#define AON_RTC_BASE (PERIPH_BASE + 0x92000) 
#define AON_RTC ((aon_rtc_regs_t *) (AON_RTC_BASE)) 
typedef struct {
    reg32_t INFRCLKDIVR; 
    reg32_t INFRCLKDIVS; 
    reg32_t INFRCLKDIVDS; 
    reg32_t VDCTL; 
    reg32_t __reserved1[6]; 
    reg32_t CLKLOADCTL; 
    reg32_t RFCCLKG; 
    reg32_t VIMSCLKG; 
    reg32_t __reserved2[2]; 
    reg32_t SECDMACLKGR; 
    reg32_t SECDMACLKGS; 
    reg32_t SECDMACLKGDS; 
    reg32_t GPIOCLKGR; 
    reg32_t GPIOCLKGS; 
    reg32_t GPIOCLKGDS; 
    reg32_t GPTCLKGR; 
    reg32_t GPTCLKGS; 
    reg32_t GPTCLKGDS; 
    reg32_t I2CCLKGR; 
    reg32_t I2CCLKGS; 
    reg32_t I2CCLKGDS; 
    reg32_t UARTCLKGR; 
    reg32_t UARTCLKGS; 
    reg32_t UARTCLKGDS; 
    reg32_t SSICLKGR; 
    reg32_t SSICLKGS; 
    reg32_t SSICLKGDS; 
    reg32_t I2SCLKGR; 
    reg32_t I2SCLKGS; 
    reg32_t I2SCLKGDS; 
    reg32_t __reserved3[9]; 
    reg32_t SYSBUSCLKDIV; 
    reg32_t CPUCLKDIV; 
    reg32_t PERBUSCPUCLKDIV; 
    reg32_t __reserved4; 
    reg32_t PERDMACLKDIV; 
    reg32_t I2SBCLKSEL; 
    reg32_t GPTCLKDIV; 
    reg32_t I2SCLKCTL; 
    reg32_t I2SMCLKDIV; 
    reg32_t I2SBCLKDIV; 
    reg32_t I2SWCLKDIV; 
    reg32_t __reserved5[4]; 
    reg32_t RESETSECDMA; 
    reg32_t RESETGPIO; 
    reg32_t RESETGPT; 
    reg32_t RESETI2C; 
    reg32_t RESETUART; 
    reg32_t RESETSSI; 
    reg32_t RESETI2S; 
    reg32_t __reserved6[8]; 
    reg32_t PDCTL0; 
    reg32_t PDCTL0RFC; 
    reg32_t PDCTL0SERIAL; 
    reg32_t PDCTL0PERIPH; 
    reg32_t __reserved7; 
    reg32_t PDSTAT0; 
    reg32_t PDSTAT0RFC; 
    reg32_t PDSTAT0SERIAL; 
    reg32_t PDSTAT0PERIPH; 
    reg32_t __reserved8[11]; 
    reg32_t PDCTL1; 
    reg32_t __reserved9; 
    reg32_t PDCTL1CPU; 
    reg32_t PDCTL1RFC; 
    reg32_t PDCTL1VIMS; 
    reg32_t __reserved10; 
    reg32_t PDSTAT1; 
    reg32_t PDSTAT1BUS; 
    reg32_t PDSTAT1RFC; 
    reg32_t PDSTAT1CPU; 
    reg32_t PDSTAT1VIMS; 
    reg32_t __reserved11[9]; 
    reg32_t RFCBITS; 
    reg32_t RFCMODESEL; 
    reg32_t RFCMODEHWOPT; 
    reg32_t __reserved12[2]; 
    reg32_t PWRPROFSTAT; 
    reg32_t __reserved13[14]; 
    reg32_t MCUSRAMCFG; 
    reg32_t __reserved14; 
    reg32_t RAMRETEN; 
    reg32_t __reserved15[27]; 
    reg32_t OSCIMSC; 
    reg32_t OSCRIS; 
    reg32_t OSCICR; 
} prcm_regs_t;
 
#define CLKLOADCTL_LOAD        0x1
#define CLKLOADCTL_LOADDONE    0x2
 
#define PDCTL0_RFC_ON       0x1
#define PDCTL0_SERIAL_ON    0x2
#define PDCTL0_PERIPH_ON    0x4
 
#define PDSTAT0_RFC_ON       0x1
#define PDSTAT0_SERIAL_ON    0x2
#define PDSTAT0_PERIPH_ON    0x4
 
#define PDCTL1_CPU_ON       0x2
#define PDCTL1_RFC_ON       0x4
#define PDCTL1_VIMS_ON      0x8
 
#define PDSTAT1_CPU_ON      0x2
#define PDSTAT1_RFC_ON      0x4
#define PDSTAT1_VIMS_ON     0x8
 
#define GPIOCLKGR_CLK_EN        0x1
#define I2CCLKGR_CLK_EN         0x1
#define UARTCLKGR_CLK_EN_UART0  0x1
#define UARTCLKGR_CLK_EN_UART1  0x2
 
#define GPIOCLKGS_CLK_EN        0x1
#define I2CCLKGS_CLK_EN         0x1
#define UARTCLKGS_CLK_EN_UART0  0x1
#define UARTCLKGS_CLK_EN_UART1  0x2
 
#define GPIOCLKGDS_CLK_EN       0x1
#define I2CCLKGDS_CLK_EN        0x1
#define UARTCLKGDS_CLK_EN_UART0 0x1
#define UARTCLKGDS_CLK_EN_UART1 0x2
#define PRCM_BASE        (PERIPH_BASE + 0x82000) 
#define PRCM_BASE_NONBUF (PERIPH_BASE_NONBUF + 0x82000) 
#define PRCM        ((prcm_regs_t *) (PRCM_BASE)) 
#define PRCM_NONBUF ((prcm_regs_t *) (PRCM_BASE_NONBUF)) 
#ifdef __cplusplus
} /* end extern "C" */
#endif