cfg_usb_otg_hs_phy_fs.h
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1 /*
2  * Copyright (C) 2019 Koen Zandberg
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
25 #include "periph_cpu.h"
26 #include "usbdev_synopsys_dwc2.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
35 #define DWC2_USB_OTG_HS_ENABLED
36 
41  {
42  .periph = USB_OTG_HS_PERIPH_BASE,
43  .type = DWC2_USB_OTG_HS,
45  .rcc_mask = RCC_AHB1ENR_OTGHSEN,
46  .irqn = OTG_HS_IRQn,
47  .ahb = AHB1,
48  .dm = GPIO_PIN(PORT_B, 14),
49  .dp = GPIO_PIN(PORT_B, 15),
50  .af = GPIO_AF12,
51  }
52 };
53 
57 #define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
58 
59 #ifdef __cplusplus
60 }
61 #endif
62 
@ PORT_B
port B
Definition: periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG FS configuration.
@ GPIO_AF12
use alternate function 12
Definition: cpu_gpio.h:114
USB OTG configuration.
uintptr_t periph
USB peripheral base address.
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_BUILTIN
on-chip FS PHY
@ DWC2_USB_OTG_HS
High speed peripheral.