cpu.h

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/*
 * Copyright (C) 2014-2015 Freie Universität Berlin
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#pragma once
 
#include "irq.h"
#include "sched.h"
#include "thread.h"
#include "cpu_conf.h" /* IWYU pragma: export */
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define STACK_CANARY_WORD   (0xE7FEE7FEu)
 
#define PROVIDES_PM_SET_LOWEST
 
#define CORTEXM_SCB_CPACR_FPU_ACCESS_FULL         (0x00f00000)
 
void cortexm_init(void);
 
static inline void cortexm_init_fpu(void)
{
    /* initialize the FPU on Cortex-M4F CPUs */
#if (defined(CPU_CORE_CORTEX_M33) || defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7)) && defined(MODULE_CORTEXM_FPU)
    /* give full access to the FPU */
    SCB->CPACR |= (uint32_t)CORTEXM_SCB_CPACR_FPU_ACCESS_FULL;
#endif
}
 
#if defined(CPU_CORTEXM_INIT_SUBFUNCTIONS) || defined(DOXYGEN)
 
void cortexm_init_isr_priorities(void);
 
void cortexm_init_misc(void);
 
#endif /* defined(CPU_CORTEXM_INIT_SUBFUNCTIONS) || defined(DOXYGEN) */
 
static inline uintptr_t cpu_get_caller_pc(void)
{
    uintptr_t lr_ptr;
    __asm__ __volatile__("mov %0, lr" : "=r"(lr_ptr));
    return lr_ptr;
}
 
static inline void cortexm_sleep_until_event(void)
{
    __WFE();
}
 
static inline void cortexm_sleep(int deep)
{
    if (deep) {
        SCB->SCR |=  (SCB_SCR_SLEEPDEEP_Msk);
    }
    else {
        SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
    }
 
    /* ensure that all memory accesses have completed and trigger sleeping */
    unsigned state = irq_disable();
    __DSB();
    __WFI();
    /* Some CPUs require an ISB after WFI to work around silicon bugs */
#if CORTEXM_ISB_REQUIRED_AFTER_WFI
    __ISB();
#endif
    irq_restore(state);
}
 
static inline void cortexm_isr_end(void)
{
    if (sched_context_switch_request) {
        thread_yield_higher();
    }
}
 
static inline void cpu_jump_to_image(uint32_t image_address)
{
    /* On Cortex-M platforms, the flash begins with:
     *
     * 1. 4 byte pointer to stack to be used at startup
     * 2. 4 byte pointer to the reset vector function
     *
     * On powerup, the CPU sets the stack pointer and starts executing the
     * reset vector.
     *
     * We're doing the same here, but we'd like to start at image_address.
     *
     * This function must be called while executing from MSP (Master Stack
     * Pointer).
     */
 
    /* set MSP */
    __set_MSP(*(uint32_t*)image_address);
 
    /* skip stack pointer */
    image_address += 4;
 
    /* load the images reset_vector address */
    uint32_t destination_address = *(uint32_t*)image_address;
 
    /* Make sure the Thumb State bit is set. */
    destination_address |= 0x1;
 
    /* Branch execution */
    __asm("BX %0" :: "r" (destination_address));
}
 
/* The following register is only present for
   Cortex-M0+, -M23, -M3, -M33, -M4 and M7 CPUs */
#if defined(CPU_CORE_CORTEX_M0PLUS) || defined(CPU_CORE_CORTEX_M23) || \
    defined(CPU_CORE_CORTEX_M3) || defined(CPU_CORE_CORTEX_M33) || \
    defined(CPU_CORE_CORTEX_M4) || defined(CPU_CORE_CORTEX_M4F) || \
    defined(CPU_CORE_CORTEX_M7)
static inline uint32_t cpu_get_image_baseaddr(void)
{
    return SCB->VTOR;
}
#endif
 
bool cpu_check_address(volatile const char *address);
 
#ifdef __cplusplus
}
#endif