fdcandev_stm32.h

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/*
 * Copyright (C) 2024 COGIP Robotics association
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include "can/candev.h"
 
#if defined(FDCAN3)
#define FDCANDEV_STM32_CHAN_NUMOF 3
#elif defined(FDCAN2)
#define FDCANDEV_STM32_CHAN_NUMOF 2
#elif defined(FDCAN1) || DOXYGEN
#define FDCANDEV_STM32_CHAN_NUMOF 1
#else
#error "FDCAN STM32: CPU not supported"
#endif
 
#define ISR_FDCAN1_IT0  isr_fdcan1_it0  
#define ISR_FDCAN1_IT1  isr_fdcan1_it1  
#define FDCAN_STM32_NB_STD_FILTER   28U 
#define FDCAN_STM32_NB_EXT_FILTER   8U  
#define FDCAN_STM32_NB_FILTER \
        (FDCAN_STM32_NB_STD_FILTER + FDCAN_STM32_NB_EXT_FILTER) 
#ifndef FDCANDEV_STM32_DEFAULT_BITRATE
#define FDCANDEV_STM32_DEFAULT_BITRATE 500000U
#endif
#ifndef FDCANDEV_STM32_DEFAULT_FD_DATA_BITRATE
#define FDCANDEV_STM32_DEFAULT_FD_DATA_BITRATE 1000000U
#endif
#ifndef FDCANDEV_STM32_DEFAULT_SPT
#define FDCANDEV_STM32_DEFAULT_SPT     875
#endif
 
typedef struct {
    FDCAN_GlobalTypeDef *can;   
    uint32_t rcc_mask;          
    gpio_t rx_pin;              
    gpio_t tx_pin;              
    gpio_af_t af;               
    bool en_deep_sleep_wake_up; 
    uint8_t it0_irqn;           
    uint8_t it1_irqn;           
    uint8_t ttcm : 1;           
    uint8_t abom : 1;           
    uint8_t awum : 1;           
    uint8_t nart : 1;           
    uint8_t rflm : 1;           
    uint8_t txfp : 1;           
    uint8_t lbkm : 1;           
    uint8_t silm : 1;           
} can_conf_t;
#define HAVE_CAN_CONF_T
 
#define FDCAN_STM32_TX_MAILBOXES 3
#define FDCAN_STM32_RX_MAILBOXES (FDCANDEV_STM32_CHAN_NUMOF * 6)
typedef struct can can_t;
#define HAVE_CAN_T
 
#define FDCAN_SRAM_MESSAGE_RAM_SIZE     0x350   
#define FDCAN_SRAM_FLESA                0x1CU   
#define FDCAN_SRAM_F0SA                 0x2CU   
#define FDCAN_SRAM_F1SA                 0x62U   
#define FDCAN_SRAM_EFSA                 0x98U   
#define FDCAN_SRAM_TBSA                 0x9EU   
#define FDCAN_SRAM_FLS_SFID1_Pos        (16U)
#define FDCAN_SRAM_FLS_SFID1_Msk        (0x7FFU << FDCAN_SRAM_FLS_SFID1_Pos)
#define FDCAN_SRAM_FLS_SFID1            FDCAN_SRAM_FLS_SFID1_Msk
#define FDCAN_SRAM_FLS_SFID2_Msk        (0x7FFU)
#define FDCAN_SRAM_FLS_SFID2            FDCAN_SRAM_FLS_SFID2_Msk
#define FDCAN_SRAM_FLS_SFT_Pos          (30U)
#define FDCAN_SRAM_FLS_SFT_Msk          (0x3U << FDCAN_SRAM_FLS_SFT_Pos)
#define FDCAN_SRAM_FLS_SFT              FDCAN_SRAM_FLS_SFT_Msk
#define FDCAN_SRAM_FLS_SFEC_Pos         (27U)
#define FDCAN_SRAM_FLS_SFEC_Msk         (0x7U << FDCAN_SRAM_FLS_SFEC_Pos)
#define FDCAN_SRAM_FLS_SFEC             FDCAN_SRAM_FLS_SFEC_Msk
#define FDCAN_SRAM_FLS_FILTER_SIZE      1U
#define FDCAN_SRAM_FLS_SFT_DISABLED     (0x3U << FDCAN_SRAM_FLS_SFT_Pos)
#define FDCAN_SRAM_FLS_SFT_CLASSIC      (0x2U << FDCAN_SRAM_FLS_SFT_Pos)
#define FDCAN_SRAM_FLS_SFEC_DISABLED    (0x0U << FDCAN_SRAM_FLS_SFEC_Pos)
#define FDCAN_SRAM_FLS_SFEC_FIFO0       (0x1U << FDCAN_SRAM_FLS_SFEC_Pos)
#define FDCAN_SRAM_FLS_SFEC_FIFO1       (0x2U << FDCAN_SRAM_FLS_SFEC_Pos)
#define FDCAN_SRAM_FLE_F0_EFID1_Msk     0x1FFFFFFFU
#define FDCAN_SRAM_FLE_F0_EFID1         FDCAN_SRAM_FLE_F0_EFID1_Msk
#define FDCAN_SRAM_FLE_F1_EFID2_Msk     0x1FFFFFFFU
#define FDCAN_SRAM_FLE_F1_EFID2         FDCAN_SRAM_FLE_F1_EFID2_Msk
#define FDCAN_SRAM_FLE_F1_EFT_Pos       30U
#define FDCAN_SRAM_FLE_F1_EFT_Msk       (0x3U << FDCAN_SRAM_FLE_F1_EFT_Pos)
#define FDCAN_SRAM_FLE_F1_EFT           FDCAN_SRAM_FLE_F1_EFT_Msk
#define FDCAN_SRAM_FLE_F0_EFEC_Pos      29U
#define FDCAN_SRAM_FLE_F0_EFEC_Msk      (0x7U << FDCAN_SRAM_FLE_F0_EFEC_Pos)
#define FDCAN_SRAM_FLE_F0_EFEC          FDCAN_SRAM_FLE_F0_EFEC_Msk
#define FDCAN_SRAM_FLE_FILTER_SIZE      2U
#define FDCAN_SRAM_FLE_F1_EFT_CLASSIC   (0x2U << FDCAN_SRAM_FLE_F1_EFT_Pos)
#define FDCAN_SRAM_FLE_F0_EFEC_DISABLED (0x0U)
#define FDCAN_SRAM_FLE_F0_EFEC_FIFO0    (0x1U << FDCAN_SRAM_FLE_F0_EFEC_Pos)
#define FDCAN_SRAM_FLE_F0_EFEC_FIFO1    (0x2U << FDCAN_SRAM_FLE_F0_EFEC_Pos)
#define FDCAN_SRAM_TXBUFFER_T0_ESI_Pos  31U
#define FDCAN_SRAM_TXBUFFER_T0_ESI_Msk  (0x1U << FDCAN_SRAM_TXBUFFER_T0_ESI_Pos)
#define FDCAN_SRAM_TXBUFFER_T0_ESI      FDCAN_SRAM_TXBUFFER_T0_ESI_Msk
#define FDCAN_SRAM_TXBUFFER_T0_XTD_Pos  30U
#define FDCAN_SRAM_TXBUFFER_T0_XTD_Msk  (0x1U << FDCAN_SRAM_TXBUFFER_T0_XTD_Pos)
#define FDCAN_SRAM_TXBUFFER_T0_XTD      FDCAN_SRAM_TXBUFFER_T0_XTD_Msk
#define FDCAN_SRAM_TXBUFFER_T0_RTR_Pos  29U
#define FDCAN_SRAM_TXBUFFER_T0_RTR_Msk  (0x1U << FDCAN_SRAM_TXBUFFER_T0_RTR_Pos)
#define FDCAN_SRAM_TXBUFFER_T0_RTR      FDCAN_SRAM_TXBUFFER_T0_RTR_Msk
#define FDCAN_SRAM_TXBUFFER_T0_ID_Pos   18U
#define FDCAN_SRAM_TXBUFFER_T1_EFC_Pos  23U
#define FDCAN_SRAM_TXBUFFER_T1_EFC_Msk  (0x1U << FDCAN_SRAM_TXBUFFER_T1_EFC_Pos)
#define FDCAN_SRAM_TXBUFFER_T1_EFC      FDCAN_SRAM_TXBUFFER_T1_EFC_Msk
#define FDCAN_SRAM_TXBUFFER_T1_FDF_Pos  21U
#define FDCAN_SRAM_TXBUFFER_T1_FDF_Msk  (0x1U << FDCAN_SRAM_TXBUFFER_T1_FDF_Pos)
#define FDCAN_SRAM_TXBUFFER_T1_FDF      FDCAN_SRAM_TXBUFFER_T1_FDF_Msk
#define FDCAN_SRAM_TXBUFFER_T1_BRS_Pos  20U
#define FDCAN_SRAM_TXBUFFER_T1_BRS_Msk  (0x1U << FDCAN_SRAM_TXBUFFER_T1_BRS_Pos)
#define FDCAN_SRAM_TXBUFFER_T1_BRS      FDCAN_SRAM_TXBUFFER_T1_BRS_Msk
#define FDCAN_SRAM_TXBUFFER_T1_DLC_Pos  16U
#define FDCAN_SRAM_TXBUFFER_T1_DLC_Msk  (0xFU << FDCAN_SRAM_TXBUFFER_T1_DLC_Pos)
#define FDCAN_SRAM_TXBUFFER_T1_DLC      FDCAN_SRAM_TXBUFFER_T1_DLC_Msk
#define FDCAN_SRAM_TXBUFFER_SIZE                18U
#define FDCAN_SRAM_TXBUFFER_T0_ESI_PASSIVE_FLAG (0x0U << FDCAN_SRAM_TXBUFFER_T0_ESI_Pos)
#define FDCAN_SRAM_TXBUFFER_T0_ESI_RECESSIVE    (0x1U << FDCAN_SRAM_TXBUFFER_T0_ESI_Pos)
#define FDCAN_SRAM_TXBUFFER_T1_EFC_DISABLE      (0x0U << FDCAN_SRAM_TXBUFFER_T1_EFC_Pos)
#define FDCAN_SRAM_TXBUFFER_T1_EFC_STORE_EVENTS (0x1U << FDCAN_SRAM_TXBUFFER_T1_EFC_Pos)
#define FDCAN_SRAM_TXBUFFER_T1_FDF_CLASSIC      (0x0U << FDCAN_SRAM_TXBUFFER_T1_FDF_Pos)
#define FDCAN_SRAM_TXBUFFER_T1_FDF_FD           (0x1U << FDCAN_SRAM_TXBUFFER_T1_FDF_Pos)
#define FDCAN_SRAM_TXBUFFER_T1_BRS_OFF          (0x0U << FDCAN_SRAM_TXBUFFER_T1_BRS_Pos)
#define FDCAN_SRAM_TXBUFFER_T1_BRS_ON           (0x1U << FDCAN_SRAM_TXBUFFER_T1_BRS_Pos)
#define FDCAN_SRAM_RXFIFO_R0_ESI_Pos    31U
#define FDCAN_SRAM_RXFIFO_R0_ESI_Msk    (0x1U << FDCAN_SRAM_RXFIFO_R0_ESI_Pos)
#define FDCAN_SRAM_RXFIFO_R0_ESI        FDCAN_SRAM_RXFIFO_R0_ESI_Msk
#define FDCAN_SRAM_RXFIFO_R0_XTD_Pos    30U
#define FDCAN_SRAM_RXFIFO_R0_XTD_Msk    (0x1U << FDCAN_SRAM_RXFIFO_R0_XTD_Pos)
#define FDCAN_SRAM_RXFIFO_R0_XTD        FDCAN_SRAM_RXFIFO_R0_XTD_Msk
#define FDCAN_SRAM_RXFIFO_R0_RTR_Pos    29U
#define FDCAN_SRAM_RXFIFO_R0_RTR_Msk    (0x1U << FDCAN_SRAM_RXFIFO_R0_RTR_Pos)
#define FDCAN_SRAM_RXFIFO_R0_RTR        FDCAN_SRAM_RXFIFO_R0_RTR_Msk
#define FDCAN_SRAM_RXFIFO_R0_ID_Pos     18U
#define FDCAN_SRAM_RXFIFO_R0_ID_Msk     0x1FFFFFFFU
#define FDCAN_SRAM_RXFIFO_R0_ID         FDCAN_SRAM_RXFIFO_R0_ID_Msk
#define FDCAN_SRAM_RXFIFO_R1_EFC_Pos    23U
#define FDCAN_SRAM_RXFIFO_R1_EFC_Msk    (0x1U << FDCAN_SRAM_RXFIFO_R1_EFC_Pos)
#define FDCAN_SRAM_RXFIFO_R1_EFC        FDCAN_SRAM_RXFIFO_R1_EFC_Msk
#define FDCAN_SRAM_RXFIFO_R1_FDF_Pos    21U
#define FDCAN_SRAM_RXFIFO_R1_FDF_Msk    (0x1U << FDCAN_SRAM_RXFIFO_R1_FDF_Pos)
#define FDCAN_SRAM_RXFIFO_R1_FDF        FDCAN_SRAM_RXFIFO_R1_FDF_Msk
#define FDCAN_SRAM_RXFIFO_R1_BRS_Pos    20U
#define FDCAN_SRAM_RXFIFO_R1_BRS_Msk    (0x1U << FDCAN_SRAM_RXFIFO_R1_BRS_Pos)
#define FDCAN_SRAM_RXFIFO_R1_BRS        FDCAN_SRAM_RXFIFO_R1_BRS_Msk
#define FDCAN_SRAM_RXFIFO_R1_DLC_Pos    16U
#define FDCAN_SRAM_RXFIFO_R1_DLC_Msk    (0xFU << FDCAN_SRAM_RXFIFO_R1_DLC_Pos)
#define FDCAN_SRAM_RXFIFO_R1_DLC        FDCAN_SRAM_RXFIFO_R1_DLC_Msk
#define FDCAN_SRAM_RXFIFO_SIZE          54U
#define FDCAN_SRAM_RXFIFO_ELEMENT_SIZE  18U
#define FDCAN_SRAM_RXFIFO_R0_ESI_PASSIVE_FLAG   (0x0U << FDCAN_SRAM_RXFIFO_R0_ESI_Pos)
#define FDCAN_SRAM_RXFIFO_R0_ESI_RECESSIVE      (0x1U << FDCAN_SRAM_RXFIFO_R0_ESI_Pos)
#define FDCAN_SRAM_RXFIFO_R1_EFC_DISABLE        (0x0U << FDCAN_SRAM_RXFIFO_R1_EFC_Pos)
#define FDCAN_SRAM_RXFIFO_R1_EFC_STORE_EVENTS   (0x1U << FDCAN_SRAM_RXFIFO_R1_EFC_Pos)
#define FDCAN_SRAM_RXFIFO_R1_FDF_CLASSIC        (0x0U << FDCAN_SRAM_RXFIFO_R1_FDF_Pos)
#define FDCAN_SRAM_RXFIFO_R1_FDF_FD             (0x1U << FDCAN_SRAM_RXFIFO_R1_FDF_Pos)
#define FDCAN_SRAM_RXFIFO_R1_BRS_OFF            (0x0U << FDCAN_SRAM_RXFIFO_R1_BRS_Pos)
#define FDCAN_SRAM_RXFIFO_R1_BRS_ON             (0x1U << FDCAN_SRAM_RXFIFO_R1_BRS_Pos)
typedef struct candev_stm32_rx_mailbox {
    can_frame_t frame[FDCAN_STM32_RX_MAILBOXES];
    int write_idx;
    int read_idx;
    int is_full;
} candev_stm32_rx_mailbox_t;
 
typedef struct candev_stm32_isr {
    int isr_tx : 3;     
    int isr_rx : 2;     
    int isr_wkup : 1;   
} candev_stm32_isr_t;
 
struct can {
    candev_t candev;                    
    const can_conf_t *conf;             
    gpio_t rx_pin;                      
    gpio_t tx_pin;                      
    gpio_af_t af;                       
    const can_frame_t
        *tx_mailbox[FDCAN_STM32_TX_MAILBOXES];  
    candev_stm32_rx_mailbox_t rx_mailbox;       
    candev_stm32_isr_t isr_flags;               
};
 
void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin,
                           gpio_af_t af);
#ifdef __cplusplus
}
#endif