periph_cpu.h

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/*
 * SPDX-FileCopyrightText: 2015 Rakendra Thapa <rakendrathapa@gmail.com>
 * SPDX-FileCopyrightText: 2017 Marc Poulhiès <dkm@kataplop.net>
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once
 
#include "cpu.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
#define GPIO_PIN(x, y) ((gpio_t)((x<<4) | y))
#ifndef DOXYGEN
#define HAVE_GPIO_MODE_T
typedef enum {
    GPIO_IN    = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD << 4)),     
    GPIO_IN_PD = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD_WPD << 4)), 
    GPIO_IN_PU = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD_WPU << 4)), 
    GPIO_OUT   = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_STD << 4)),    
    GPIO_OD    = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_OD << 4)),     
    GPIO_OD_PU = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_OD_WPU << 4)), 
} gpio_mode_t;
#endif /* ndef DOXYGEN */
 
#define HAVE_GPIO_DIR_T
typedef enum {
  GPIO_DIR_IN = GPIO_DIR_MODE_IN,       
  GPIO_DIR_OUT = GPIO_DIR_MODE_OUT      
} gpio_dir_t;
#ifndef DOXYGEN
#define HAVE_GPIO_FLANK_T
typedef enum {
    GPIO_FALLING = GPIO_FALLING_EDGE,    
    GPIO_RISING = GPIO_RISING_EDGE,      
    GPIO_BOTH = GPIO_BOTH_EDGES          
} gpio_flank_t;
#endif /* ndef DOXYGEN */
 
enum {
  PORT_A = 0,       
  PORT_B = 1,       
  PORT_C = 2,       
  PORT_D = 3,       
  PORT_E = 4,       
  PORT_F = 5,       
};
 
#ifndef DOXYGEN
#define HAVE_ADC_RES_T
typedef enum {
    ADC_RES_6BIT  = 0xa00,            
    ADC_RES_8BIT  = 0xb00,            
    ADC_RES_10BIT = ADC_RES_10BIT_S,  
    ADC_RES_12BIT = ADC_RES_12BIT_S,  
    ADC_RES_14BIT = 0xc00,            
    ADC_RES_16BIT = 0xd00,            
} adc_res_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    uint32_t dev;       
    uint32_t max;       
    int irqn;           
    uint32_t sysctl;    
    uint32_t intbase;   
    int channels;       
} timer_conf_t;
 
#define SPI_HWCS(x)     (UINT_MAX - 1)
 
typedef struct {
    unsigned long ssi_sysctl;          
    unsigned long ssi_base;            
    unsigned long gpio_sysctl;         
    unsigned long gpio_port;           
    struct {
        unsigned long clk;             
        unsigned long fss;             
        unsigned long rx;              
        unsigned long tx;              
        unsigned long mask;            
    } pins;                            
} spi_conf_t;
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
#define PERIPH_SPI_NEEDS_TRANSFER_REG 1
#define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
#define PERIPH_SPI_NEEDS_INIT_CS 1
#ifndef DOXYGEN
#define HAVE_SPI_CLK_T 1
typedef enum {
    SPI_CLK_100KHZ = 100000,        
    SPI_CLK_400KHZ = 400000,        
    SPI_CLK_1MHZ   = 1000000,       
    SPI_CLK_4MHZ   = 4000000,       
    SPI_CLK_5MHZ   = 5000000,       
    SPI_CLK_10MHZ  = 10000000,      
} spi_clk_t;
#define HAVE_SPI_MODE_T 1
typedef enum {
    SPI_MODE_0 = SSI_FRF_MOTO_MODE_0,       
    SPI_MODE_1 = SSI_FRF_MOTO_MODE_1,       
    SPI_MODE_2 = SSI_FRF_MOTO_MODE_2,       
    SPI_MODE_3 = SSI_FRF_MOTO_MODE_0,       
} spi_mode_t;
#endif /* ndef DOXYGEN */
 
#ifdef __cplusplus
}
#endif