PRCM registers. More...
PRCM registers.
Definition at line 232 of file cc26x0_cc13x0_prcm.h.
#include <cc26x0_cc13x0_prcm.h>
Data Fields | |
| reg32_t | INFRCLKDIVR |
| infrastructure clock division factor for run mode | |
| reg32_t | INFRCLKDIVS |
| infrastructure clock division factor for sleep mode | |
| reg32_t | INFRCLKDIVDS |
| infrastructure clock division factor for deep sleep mode | |
| reg32_t | VDCTL |
| MCU voltage domain control. | |
| reg32_t | __reserved1 [6] |
| Reserved. | |
| reg32_t | CLKLOADCTL |
| clock load control | |
| reg32_t | RFCCLKG |
| RFC clock gate. | |
| reg32_t | VIMSCLKG |
| VIMS clock gate. | |
| reg32_t | __reserved2 [2] |
| Reserved. | |
| reg32_t | SECDMACLKGR |
| TRNG, CRYPTO, and UDMA clock gate for run mode. | |
| reg32_t | SECDMACLKGS |
| TRNG, CRYPTO, and UDMA clock gate for sleep mode. | |
| reg32_t | SECDMACLKGDS |
| TRNG, CRYPTO, and UDMA clock gate for deep sleep mode. | |
| reg32_t | GPIOCLKGR |
| GPIO clock gate for run mode. | |
| reg32_t | GPIOCLKGS |
| GPIO clock gate for sleep mode. | |
| reg32_t | GPIOCLKGDS |
| GPIO clock gate for deep sleep mode. | |
| reg32_t | GPTCLKGR |
| GPT clock gate for run mode. | |
| reg32_t | GPTCLKGS |
| GPT clock gate for sleep mode. | |
| reg32_t | GPTCLKGDS |
| GPT clock gate for deep sleep mode. | |
| reg32_t | I2CCLKGR |
| I2C clock gate for run mode. | |
| reg32_t | I2CCLKGS |
| I2C clock gate for sleep mode. | |
| reg32_t | I2CCLKGDS |
| I2C clock gate for deep sleep mode. | |
| reg32_t | UARTCLKGR |
| UART clock gate for run mode. | |
| reg32_t | UARTCLKGS |
| UART clock gate for sleep mode. | |
| reg32_t | UARTCLKGDS |
| UART clock gate for deep sleep mode. | |
| reg32_t | SSICLKGR |
| SSI clock gate for run mode. | |
| reg32_t | SSICLKGS |
| SSI clock gate for sleep mode. | |
| reg32_t | SSICLKGDS |
| SSI clock gate for deep sleep mode. | |
| reg32_t | I2SCLKGR |
| I2S clock gate for run mode. | |
| reg32_t | I2SCLKGS |
| I2S clock gate for sleep mode. | |
| reg32_t | I2SCLKGDS |
| I2S clock gate for deep sleep mode. | |
| reg32_t | __reserved3 [10] |
| Reserved. | |
| reg32_t | CPUCLKDIV |
| CPU clock division factor. | |
| reg32_t | __reserved4 [3] |
| Reserved. | |
| reg32_t | I2SBCLKSEL |
| I2S clock select. | |
| reg32_t | GPTCLKDIV |
| GPT scalar. | |
| reg32_t | I2SCLKCTL |
| I2S clock control. | |
| reg32_t | I2SMCLKDIV |
| MCLK division ratio. | |
| reg32_t | I2SBCLKDIV |
| BCLK division ratio. | |
| reg32_t | I2SWCLKDIV |
| WCLK division ratio. | |
| reg32_t | __reserved5 [11] |
| Reserved. | |
| reg32_t | SWRESET |
| SW initiated resets. | |
| reg32_t | WARMRESET |
| WARM reset control and status. | |
| reg32_t | __reserved6 [6] |
| Reserved. | |
| reg32_t | PDCTL0 |
| power domain control | |
| reg32_t | PDCTL0RFC |
| RFC power domain control. | |
| reg32_t | PDCTL0SERIAL |
| SERIAL power domain control. | |
| reg32_t | PDCTL0PERIPH |
| PERIPH power domain control. | |
| reg32_t | __reserved7 |
| Reserved. | |
| reg32_t | PDSTAT0 |
| power domain status | |
| reg32_t | PDSTAT0RFC |
| RFC power domain status. | |
| reg32_t | PDSTAT0SERIAL |
| SERIAL power domain status. | |
| reg32_t | PDSTAT0PERIPH |
| PERIPH power domain status. | |
| reg32_t | __reserved8 [11] |
| Reserved. | |
| reg32_t | PDCTL1 |
| power domain control | |
| reg32_t | __reserved9 |
| power domain control | |
| reg32_t | PDCTL1CPU |
| CPU power domain control. | |
| reg32_t | PDCTL1RFC |
| RFC power domain control. | |
| reg32_t | PDCTL1VIMS |
| VIMS power domain control. | |
| reg32_t | __reserved10 |
| Reserved. | |
| reg32_t | PDSTAT1 |
| power domain status | |
| reg32_t | PDSTAT1BUS |
| BUS power domain status. | |
| reg32_t | PDSTAT1RFC |
| RFC power domain status. | |
| reg32_t | PDSTAT1CPU |
| CPU power domain status. | |
| reg32_t | PDSTAT1VIMS |
| VIMS power domain status. | |
| reg32_t | __reserved11 [10] |
| Reserved. | |
| reg32_t | RFCMODESEL |
| selected RFC mode | |
| reg32_t | __reserved12 [20] |
| Reserved. | |
| reg32_t | RAMRETEN |
| memory retention control | |
| reg32_t | __reserved13 |
| Reserved. | |
| reg32_t | PDRETEN |
| power domain retention (undocumented) | |
| reg32_t | __reserved14 [8] |
| Reserved. | |
| reg32_t | RAMHWOPT |
| undocumented | |
| reg32_t | SYSBUSCLKDIV |
| System bus clock division factor. | |
| reg32_t | PERBUSCPUCLKDIV |
| Peripheral bus division factor. | |
| reg32_t | PERDMACLKDIV |
| DMA clock division factor. | |
| reg32_t | RESETSECDMA |
| Reset SEC and UDMA. | |
| reg32_t | RESETGPIO |
| Reset GPIO. | |
| reg32_t | RESETGPT |
| Reset GPTs. | |
| reg32_t | RESETI2C |
| Reset I2C. | |
| reg32_t | RESETUART |
| Reset UART. | |
| reg32_t | RESETSSI |
| Reset SSI. | |
| reg32_t | RESETI2S |
| Reset I2S. | |
| reg32_t | RFCBITS |
| Control to RFC. | |
| reg32_t | RFCMODEHWOPT |
| allowed RFC modes | |
| reg32_t | PWRPROFSTAT |
| power profiler register | |
| reg32_t | MCUSRAMCFG |
| MCU SRAM configuration. | |
| reg32_t | __reserved15 [27] |
| Reserved. | |
| reg32_t | OSCIMSC |
| oscillator interrupt mask | |
| reg32_t | OSCRIS |
| oscillator raw interrupt status | |
| reg32_t | OSCICR |
| oscillator raw interrupt clear | |