periph_cpu_common.h
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1 /*
2  * Copyright (C) 2015 HAW Hamburg
3  * 2016 Freie Universität Berlin
4  * 2016 INRIA
5  * 2023 Hugues Larrive
6  *
7  * This file is subject to the terms and conditions of the GNU Lesser
8  * General Public License v2.1. See the file LICENSE in the top level
9  * directory for more details.
10  */
11 
12 #pragma once
13 
27 #include "cpu.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
37 #define CPUID_LEN (4U)
40 #ifndef DOXYGEN
45 #define HAVE_GPIO_T
46 typedef uint8_t gpio_t;
48 #endif
49 
53 #define GPIO_UNDEF (0xff)
54 
58 #define GPIO_PIN(x, y) ((x << 4) | y)
59 
65 #if (defined(OCF1A) && defined(OCF1B) && (OCF1A > OCF1B)) \
66  || (defined(PUD) && (PUD != 4)) || (defined(INT0) && (INT0 == 6))
67  /* match with 65 devices against 61 for (PORTB == _SFR_IO8(0x18)) which
68  * did not work here anyway */
69 #define GPIO_PORT_DESCENDENT
70 #endif
71 
72 #ifdef GPIO_PORT_DESCENDENT
73 #ifdef _AVR_ATTINY1634_H_INCLUDED
74 /* the only one that requires particular treatment! */
75 #define ATMEGA_GPIO_BASE_A 0x2F
76 #else
77 /* all other port descendent, including :
78  - _AVR_IO8534_ (only have port A but with 0x1B address) ;
79  - _AVR_IOAT94K_H_ (only have ports D and E) ;
80  - _AVR_IOTN28_H_ (only have ports A and D). */
81 #define ATMEGA_GPIO_BASE_A 0x39
82 #endif /* _AVR_ATTINY1634_H_INCLUDED */
83 #else /* !GPIO_PORT_DESCENDENT */
84 #define ATMEGA_GPIO_BASE_A 0x20
85 #endif /* GPIO_PORT_DESCENDENT */
91 #define ATMEGA_GPIO_BASE_G (ATMEGA_GPIO_BASE_A + ATMEGA_GPIO_SIZE * ('G' - 'A'))
97 #define ATMEGA_GPIO_BASE_H (0x100)
101 #define ATMEGA_GPIO_SIZE (0x03)
102 
103 #if defined(DOXYGEN)
107 #define GPIO_EXT_INT_NUMOF <CPU_SPECIFIC>
108 #elif defined(INT7_vect)
109 #define GPIO_EXT_INT_NUMOF (8U)
110 #elif defined(INT6_vect)
111 #define GPIO_EXT_INT_NUMOF (7U)
112 #elif defined(INT5_vect)
113 #define GPIO_EXT_INT_NUMOF (6U)
114 #elif defined(INT4_vect)
115 #define GPIO_EXT_INT_NUMOF (5U)
116 #elif defined(INT3_vect)
117 #define GPIO_EXT_INT_NUMOF (4U)
118 #elif defined(INT2_vect)
119 #define GPIO_EXT_INT_NUMOF (3U)
120 #else
121 #define GPIO_EXT_INT_NUMOF (2U)
122 #endif
123 
128 typedef struct {
137  volatile uint8_t pin;
142  volatile uint8_t ddr;
150  volatile uint8_t port;
152 
158 static inline atmega_gpio_port_t *atmega_gpio_port(uint8_t port_num)
159 {
160  static const uintptr_t base_addr = (uintptr_t)ATMEGA_GPIO_BASE_A;
161 #ifdef GPIO_PORT_DESCENDENT
162  uintptr_t res = base_addr - port_num * sizeof(atmega_gpio_port_t);
163 #else
164  uintptr_t res = base_addr + port_num * sizeof(atmega_gpio_port_t);
165 #endif
166  /* GPIO ports up to (including) G are mapped in the I/O address space,
167  * port H and higher (if present) are mapped in a different contiguous
168  * region afterwards (e.g. 0x100 for ATmega2560). */
169 #ifdef PORTH
170  if (port_num > 'G'-'A') {
171  static const uintptr_t offset = ATMEGA_GPIO_BASE_H - ATMEGA_GPIO_BASE_G;
172  res += offset;
173  }
174 #endif
175 
176  return (atmega_gpio_port_t *)res;
177 }
178 
179 #ifndef DOXYGEN
189 #define HAVE_GPIO_FLANK_T
190 typedef enum {
191  GPIO_LOW,
192  GPIO_BOTH,
193  GPIO_FALLING,
194  GPIO_RISING,
195 } gpio_flank_t;
197 #endif /* ndef DOXYGEN */
198 
199 #ifndef DOXYGEN /* BEGIN: GPIO LL overwrites */
200 #define HAVE_GPIO_SLEW_T
201 typedef enum {
202  GPIO_SLEW_SLOWEST = 0,
203  GPIO_SLEW_SLOW = 0,
204  GPIO_SLEW_FAST = 0,
205  GPIO_SLEW_FASTEST = 0,
206 } gpio_slew_t;
207 
208 #define HAVE_GPIO_PULL_STRENGTH_T
209 typedef enum {
210  GPIO_PULL_WEAKEST = 0,
211  GPIO_PULL_WEAK = 0,
212  GPIO_PULL_STRONG = 0,
215 
216 #define HAVE_GPIO_DRIVE_STRENGTH_T
217 typedef enum {
218  GPIO_DRIVE_WEAKEST = 0,
219  GPIO_DRIVE_WEAK = 0,
220  GPIO_DRIVE_STRONG = 0,
223 
224 #define HAVE_GPIO_IRQ_TRIG_T
225 typedef enum {
226  GPIO_TRIGGER_LEVEL_LOW = 0x00,
227  GPIO_TRIGGER_EDGE_BOTH = 0x01,
230  GPIO_TRIGGER_LEVEL_HIGH = 0xff,
232 
233 #define HAVE_GPIO_STATE_T
234 typedef enum {
235  GPIO_INPUT,
241 } gpio_state_t;
242 
243 #define HAVE_GPIO_LL_PREPARE_WRITE_ALL_PINS
244 #define HAVE_GPIO_LL_PREPARE_WRITE
245 
246 #endif /* END: GPIO LL overwrites */
247 
252 #define PERIPH_SPI_NEEDS_INIT_CS
253 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
254 #define PERIPH_SPI_NEEDS_TRANSFER_REG
255 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
258 #ifndef DOXYGEN
265 #define SPI_MODE_SEL(pol, pha) ((pol << 3) | (pha << 2))
266 
274 #define HAVE_SPI_MODE_T
275 typedef enum {
276  SPI_MODE_0 = SPI_MODE_SEL(0, 0),
277  SPI_MODE_1 = SPI_MODE_SEL(0, 1),
278  SPI_MODE_2 = SPI_MODE_SEL(1, 0),
279  SPI_MODE_3 = SPI_MODE_SEL(1, 1)
280 } spi_mode_t;
289 #define SPI_CLK_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0)
290 
297 #define HAVE_SPI_CLK_T
298 typedef enum {
299  SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1),
300  SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0),
301  SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1),
302  SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0),
303  SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0)
304 } spi_clk_t;
306 #endif /* ifndef DOXYGEN */
307 
312 typedef enum {
315 } timer_div_t;
322 typedef struct {
324  gpio_t pin_ch[2];
326 } pwm_conf_t;
332 #define PERIPH_TIMER_PROVIDES_SET
333 
337 #define EEPROM_CLEAR_BYTE (0xff)
338 
343 #define NWDT_TIME_LOWER_LIMIT (1)
344 #define NWDT_TIME_UPPER_LIMIT (8192U)
350 #define WDT_HAS_STOP (1)
351 
356 #if defined(SCCR0) && !defined(RTT_BACKEND_SC)
357 #define RTT_BACKEND_SC (1)
358 #endif
359 
360 #if RTT_BACKEND_SC
361 /* For MCU with MAC symbol counter */
362 #ifndef RTT_MAX_VALUE
363 #define RTT_MAX_VALUE (0xFFFFFFFFUL) /* 32-bit timer */
364 #endif
365 
366 #ifndef RTT_FREQUENCY
367 #define RTT_FREQUENCY (62500UL) /* in Hz. */
368 #endif
369 
370 #else
371 /* For MCU without MAC symbol counter */
372 #ifndef RTT_MAX_VALUE
373 #define RTT_MAX_VALUE (0x00FFFFFF) /* 24-bit timer */
374 #endif
375 /* possible values: 32, 128, 256, 512, 1024, 4096, 32768 */
376 #ifndef RTT_FREQUENCY
377 #define RTT_FREQUENCY (1024U) /* in Hz. */
378 #endif
379 #endif
382 #ifdef __cplusplus
383 }
384 #endif
385 
#define ATMEGA_GPIO_BASE_H
Base of the GPIO registers of the second memory region (port >= H)
#define ATMEGA_GPIO_BASE_A
Base of the GPIO registers as memory address.
timer_div_t
@ TIMER_DIV1_8_32_64_128_256_1024
1/{1,8,32,64,128,256,1024}
@ TIMER_DIV1_8_64_128_1024
1/{1,8,64,128,1024}
#define ATMEGA_GPIO_BASE_G
Base of the GPIO port G register as memory address.
static atmega_gpio_port_t * atmega_gpio_port(uint8_t port_num)
Get the GPIO PORT registers of the given GPIO PORT.
spi_clk_t
Definition: periph_cpu.h:351
gpio_irq_trig_t
Definition of possible IRQ triggers.
Definition: gpio_ll_irq.h:71
@ GPIO_TRIGGER_EDGE_FALLING
edge triggered IRQ on falling flanks only
Definition: gpio_ll_irq.h:72
@ GPIO_TRIGGER_LEVEL_HIGH
level triggered IRQ on high input
Definition: gpio_ll_irq.h:77
@ GPIO_TRIGGER_EDGE_RISING
edge triggered IRQ on rising flanks only
Definition: gpio_ll_irq.h:74
@ GPIO_TRIGGER_EDGE_BOTH
edge triggered IRQ on falling AND rising flanks
Definition: gpio_ll_irq.h:75
@ GPIO_TRIGGER_LEVEL_LOW
level triggered IRQ on low input
Definition: gpio_ll_irq.h:78
gpio_pull_strength_t
Enumeration of pull resistor values.
Definition: gpio_ll.h:275
gpio_state_t
Enumeration of GPIO states (direction)
Definition: gpio_ll.h:165
gpio_slew_t
Enumeration of slew rate settings.
Definition: gpio_ll.h:339
gpio_drive_strength_t
Enumeration of drive strength options.
Definition: gpio_ll.h:306
@ GPIO_PULL_WEAKEST
Use the weakest (highest Ohm value) resistor.
Definition: gpio_ll.h:276
@ GPIO_PULL_WEAK
Use a weak pull resistor.
Definition: gpio_ll.h:277
@ GPIO_PULL_STRONG
Use a strong pull resistor.
Definition: gpio_ll.h:278
@ GPIO_PULL_STRONGEST
Use the strongest pull resistor.
Definition: gpio_ll.h:279
@ GPIO_OUTPUT_OPEN_SOURCE
Use pin as output in open emitter configuration.
Definition: gpio_ll.h:202
@ GPIO_USED_BY_PERIPHERAL
The GPIO pin is used by a peripheral.
Definition: gpio_ll.h:221
@ GPIO_OUTPUT_OPEN_DRAIN
Use pin as output in open collector configuration.
Definition: gpio_ll.h:189
@ GPIO_OUTPUT_PUSH_PULL
Use pin as output in push-pull configuration.
Definition: gpio_ll.h:176
@ GPIO_DISCONNECT
Disconnect pin from all peripherals.
Definition: gpio_ll.h:249
@ GPIO_INPUT
Use pin as input.
Definition: gpio_ll.h:208
@ GPIO_SLEW_SLOWEST
let the output voltage level rise/fall as slow as possible
Definition: gpio_ll.h:340
@ GPIO_SLEW_FAST
let the output voltage level rise/fall fast
Definition: gpio_ll.h:343
@ GPIO_SLEW_SLOW
let the output voltage level rise/fall slowly
Definition: gpio_ll.h:342
@ GPIO_SLEW_FASTEST
let the output voltage level rise/fall as fast as possible
Definition: gpio_ll.h:344
@ GPIO_DRIVE_STRONG
Use a strong drive strength.
Definition: gpio_ll.h:309
@ GPIO_DRIVE_WEAK
Use a weak drive strength.
Definition: gpio_ll.h:308
@ GPIO_DRIVE_STRONGEST
Use the strongest drive strength.
Definition: gpio_ll.h:310
@ GPIO_DRIVE_WEAKEST
Use the weakest drive strength.
Definition: gpio_ll.h:307
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:91
@ GPIO_FALLING
emit interrupt on falling flank
@ GPIO_RISING
emit interrupt on rising flank
@ GPIO_BOTH
not supported -> random value
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition: periph_cpu.h:43
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition: periph_cpu.h:45
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition: periph_cpu.h:44
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition: periph_cpu.h:46
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition: periph_cpu.h:356
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition: periph_cpu.h:355
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition: periph_cpu.h:353
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition: periph_cpu.h:354
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition: periph_cpu.h:352
spi_mode_t
Support SPI modes.
Definition: periph_cpu.h:42
gpio_flank_t
Enumeration of supported GPIO flanks.
Structure describing the memory layout of the registers of a GPIO port on ATmega MCUs.
volatile uint8_t port
Read/write the state of GPIO pins using the Port Data Register.
volatile uint8_t pin
Toggle bits in the port register.
volatile uint8_t ddr
Configure pins as output (1) or input (0) using the Data Direction Register.
8-bit timer register map
PWM device configuration.
timer_div_t div
Timer divider mask.
mini_timer_t * dev
Timer used.