periph_conf.h
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1 /*
2  * Copyright (C) 2024 ML!PA Consulting GmbH
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
21 #include "periph_cpu.h"
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
31 #ifndef CLOCK_CORECLOCK
32 #define CLOCK_CORECLOCK MHZ(120)
33 #endif
40 #define EXTERNAL_OSC32_SOURCE 1
41 #define INTERNAL_OSC32_SOURCE 0
42 #define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE 0
49 #define USE_VREG_BUCK (1)
50 
55 #define ADC_GCLK_SRC SAM0_GCLK_PERIPH
56 #define ADC_PRESCALER ADC_CTRLA_PRESCALER_DIV8
57 #define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG(0x18u)
58 #define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
59 
60 static const adc_conf_chan_t adc_channels[] = {
61  /* port, pin, muxpos, dev */
62  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA02, .dev = ADC0 }, /* A0 */
63  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA05, .dev = ADC0 }, /* A1 */
64  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA06, .dev = ADC0 }, /* A2 */
65  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA04, .dev = ADC0 }, /* A3 */
66  { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB08, .dev = ADC1 }, /* A4 */
67  { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB09, .dev = ADC1 }, /* A5 */
68 };
69 
70 #define ADC_NUMOF ARRAY_SIZE(adc_channels)
77  /* Must not exceed 12 MHz */
78 #define DAC_CLOCK SAM0_GCLK_TIMER
79  /* Use external reference voltage on PA03 */
80  /* (A solder jumper connects PA03 to 3V3 on the
81  * back of the board. We assume the jumper has
82  * not been cut.) */
83 #define DAC_VREF DAC_CTRLB_REFSEL_VREFPU
90 static const i2c_conf_t i2c_config[] = {
91  {
92  .dev = &(SERCOM5->I2CM),
93  .speed = I2C_SPEED_NORMAL,
94  .scl_pin = GPIO_PIN(PB, 3), /* D: SERCOM5.1 */
95  .sda_pin = GPIO_PIN(PB, 2), /* D: SERCOM5.0 */
96  .mux = GPIO_MUX_D,
97  .gclk_src = SAM0_GCLK_PERIPH,
98  .flags = I2C_FLAG_NONE
99  },
100 };
101 
102 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
109 #ifndef RTT_FREQUENCY
110 #define RTT_FREQUENCY (32768U)
111 #endif
118 static const tc32_conf_t timer_config[] = {
119  { /* Timer 0 - System Clock */
120  .dev = TC0,
121  .irq = TC0_IRQn,
122  .mclk = &MCLK->APBAMASK.reg,
123  .mclk_mask = MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1,
124  .gclk_id = TC0_GCLK_ID,
125  .gclk_src = SAM0_GCLK_TIMER,
126  .flags = TC_CTRLA_MODE_COUNT32,
127  },
128  { /* Timer 1 */
129  .dev = TC2,
130  .irq = TC2_IRQn,
131  .mclk = &MCLK->APBBMASK.reg,
132  .mclk_mask = MCLK_APBBMASK_TC2 | MCLK_APBBMASK_TC3,
133  .gclk_id = TC2_GCLK_ID,
134  .gclk_src = SAM0_GCLK_TIMER,
135  .flags = TC_CTRLA_MODE_COUNT32,
136  }
137 };
138 
139 /* Timer 0 configuration */
140 #define TIMER_0_CHANNELS 2
141 #define TIMER_0_ISR isr_tc0
142 
143 /* Timer 1 configuration */
144 #define TIMER_1_CHANNELS 2
145 #define TIMER_1_ISR isr_tc2
146 
147 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
154 static const spi_conf_t spi_config[] = {
155  { /* SPI on ISP */
156  .dev = &(SERCOM2->SPI),
157  .miso_pin = GPIO_PIN(PA, 14), /* C: SERCOM2.2, D: SERCOM4.2 */
158  .mosi_pin = GPIO_PIN(PA, 12), /* C: SERCOM2.0, D: SERCOM4.1 */
159  .clk_pin = GPIO_PIN(PA, 13), /* C: SERCOM2.1, D: SERCOM4.0 */
160  .miso_mux = GPIO_MUX_C,
161  .mosi_mux = GPIO_MUX_C,
162  .clk_mux = GPIO_MUX_C,
163  .miso_pad = SPI_PAD_MISO_2,
164  .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
165  .gclk_src = SAM0_GCLK_PERIPH,
166 #if MODULE_PERIPH_DMA
167  .tx_trigger = SERCOM2_DMAC_ID_TX,
168  .rx_trigger = SERCOM2_DMAC_ID_RX,
169 #endif
170  },
171 #if !MODULE_PERIPH_UART
172  { /* D11=MOSI, D12=MISO, D13=SCK */
173  .dev = &(SERCOM3->SPI),
174  .miso_pin = GPIO_PIN(PA, 17), /* C: SERCOM1.1, D: SERCOM3.0 */
175  .mosi_pin = GPIO_PIN(PA, 19), /* C: SERCOM1.3, D: SERCOM3.3 */
176  .clk_pin = GPIO_PIN(PA, 16), /* C: SERCOM1.0, D: SERCOM3.1 */
177  .miso_mux = GPIO_MUX_D,
178  .mosi_mux = GPIO_MUX_D,
179  .clk_mux = GPIO_MUX_D,
180  .miso_pad = SPI_PAD_MISO_0,
181  .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
182  .gclk_src = SAM0_GCLK_PERIPH,
183 # if MODULE_PERIPH_DMA
184  .tx_trigger = SERCOM3_DMAC_ID_TX,
185  .rx_trigger = SERCOM3_DMAC_ID_RX,
186 # endif
187  },
188 #endif
189 #if MODULE_PERIPH_SPI_ON_QSPI
190  { /* QSPI in SPI mode */
191  .dev = QSPI,
192  .miso_pin = SAM0_QSPI_PIN_DATA_1,
193  .mosi_pin = SAM0_QSPI_PIN_DATA_0,
194  .clk_pin = SAM0_QSPI_PIN_CLK,
195  .miso_mux = SAM0_QSPI_MUX,
196  .mosi_mux = SAM0_QSPI_MUX,
197  .clk_mux = SAM0_QSPI_MUX,
198  .miso_pad = SPI_PAD_MISO_0, /* unused */
199  .mosi_pad = SPI_PAD_MOSI_0_SCK_1, /* unused */
200  .gclk_src = SAM0_GCLK_MAIN, /* unused */
201 # if MODULE_PERIPH_DMA
202  .tx_trigger = QSPI_DMAC_ID_TX,
203  .rx_trigger = QSPI_DMAC_ID_RX,
204 # endif
205  },
206 #endif
207 };
208 
209 #define SPI_NUMOF ARRAY_SIZE(spi_config)
216 static const sam0_common_usb_config_t sam_usbdev_config[] = {
217  {
218  .dm = GPIO_PIN(PA, 24),
219  .dp = GPIO_PIN(PA, 25),
220  .d_mux = GPIO_MUX_H,
221  .device = &USB->DEVICE,
222  .gclk_src = SAM0_GCLK_PERIPH,
223  }
224 };
231 static const uart_conf_t uart_config[] = {
232 /* The UART pins can be routed to SERCOM3 (used by SPI) or
233  * SERCOM5 (used by I2C). The pad configuration for SERCOM5
234  * is impossible, as TXD cannot be routed to pad 1.
235  * Hence, we let periph_spi and periph_uart conflict in
236  * Makefile.features.
237  */
238  /* D0 = RXD, D1 = TXD */
239  {
240  .dev = &SERCOM3->USART,
241  .rx_pin = GPIO_PIN(PA, 23), /* C: SERCOM3.1, D: SERCOM5.0 */
242  .tx_pin = GPIO_PIN(PA, 22), /* C: SERCOM3.0, D: SERCOM5.1 */
243  #ifdef MODULE_PERIPH_UART_HW_FC
244  .rts_pin = GPIO_UNDEF,
245  .cts_pin = GPIO_UNDEF,
246  #endif
247  .mux = GPIO_MUX_C,
248  .rx_pad = UART_PAD_RX_1,
249  .tx_pad = UART_PAD_TX_0,
250  .flags = UART_FLAG_NONE,
251  .gclk_src = SAM0_GCLK_PERIPH,
252  },
253 };
254 
255 /* interrupt function name mapping */
256 #define UART_0_ISR isr_sercom3_2
257 #define UART_0_ISR_TX isr_sercom3_0
258 
259 #define UART_NUMOF ARRAY_SIZE(uart_config)
262 #ifdef __cplusplus
263 }
264 #endif
265 
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
static const gpio_t adc_channels[]
Static array with declared ADC channels.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
@ UART_PAD_RX_1
select pad 1
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_2
use pad 2 for MISO line
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0
select pad 0
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_3_SCK_1
use pad 3 for MOSI, pad 1 for SCK
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define ADC1_INPUTCTRL_MUXPOS_PB09
Alias for AIN1.
Definition: periph_cpu.h:143
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition: periph_cpu.h:73
#define ADC0_INPUTCTRL_MUXPOS_PA04
Alias for AIN4.
Definition: periph_cpu.h:129
#define ADC1_INPUTCTRL_MUXPOS_PB08
Alias for AIN0.
Definition: periph_cpu.h:142
#define SAM0_QSPI_PIN_CLK
Clock
Definition: periph_cpu.h:268
#define ADC0_INPUTCTRL_MUXPOS_PA05
Alias for AIN5.
Definition: periph_cpu.h:130
#define SAM0_QSPI_PIN_DATA_0
D0 / MOSI
Definition: periph_cpu.h:270
#define SAM0_QSPI_PIN_DATA_1
D1 / MISO
Definition: periph_cpu.h:271
#define SAM0_QSPI_MUX
QSPI mux
Definition: periph_cpu.h:274
#define ADC0_INPUTCTRL_MUXPOS_PA06
Alias for AIN6.
Definition: periph_cpu.h:131
#define ADC0_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition: periph_cpu.h:125
#define SAM0_GCLK_PERIPH
12-48 MHz (DFLL) clock
Definition: periph_cpu.h:81
@ SAM0_GCLK_TIMER
4/8MHz clock for timers
Definition: periph_cpu.h:70
ADC Channel Configuration.
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
USB peripheral parameters.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218