periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universität Berlin
3  * 2015 PHYTEC Messtechnik GmbH
4  * 2023 Hugues Larrive
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser General
7  * Public License v2.1. See the file LICENSE in the top level directory for more
8  * details.
9  */
10 
11 #pragma once
12 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C"
28 {
29 #endif
30 
35 static const clock_config_t clock_config = {
36  /*
37  * This configuration results in the system running from the PLL output with
38  * the following clock frequencies:
39  * Core: 60 MHz
40  * Bus: 60 MHz
41  * Flex: 20 MHz
42  * Flash: 20 MHz
43  */
44  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
45  SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
46  .rtc_clc = 0, /* External load caps on board */
47  .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
48  .clock_flags =
49  /* No OSC0_EN, use EXTAL directly without OSC0 */
50  KINETIS_CLOCK_RTCOSC_EN |
51  KINETIS_CLOCK_USE_FAST_IRC |
52  0,
53  .default_mode = KINETIS_MCG_MODE_PEE,
54  /* The board has an external RMII (Ethernet) clock which drives the ERC at 50 MHz */
55  .erc_range = KINETIS_MCG_ERC_RANGE_VERY_HIGH,
56  .osc_clc = 0, /* External load caps on board */
57  .oscsel = MCG_C7_OSCSEL(0), /* Use EXTAL for external clock */
58  .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
59  .fll_frdiv = MCG_C1_FRDIV(0b111), /* Divide by 1536 => FLL input 32252 Hz */
60  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
61  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 62.5 MHz */
62  .pll_prdiv = MCG_C5_PRDIV0(0b10011), /* Divide by 20 */
63  .pll_vdiv = MCG_C6_VDIV0(0b00000), /* Multiply by 24 => PLL freq = 60 MHz */
64 };
65 #define CLOCK_CORECLOCK (60000000ul)
66 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
73 #define PIT_NUMOF (2U)
74 #define PIT_CONFIG { \
75  { \
76  .prescaler_ch = 0, \
77  .count_ch = 1, \
78  }, \
79  { \
80  .prescaler_ch = 2, \
81  .count_ch = 3, \
82  }, \
83  }
84 #define LPTMR_NUMOF (1U)
85 #define LPTMR_CONFIG { \
86  { \
87  .dev = LPTMR0, \
88  .irqn = LPTMR0_IRQn, \
89  .src = 2, \
90  .base_freq = 32768u, \
91  }, \
92 }
93 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
94 
95 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
96 #define PIT_ISR_0 isr_pit1
97 #define PIT_ISR_1 isr_pit3
98 #define LPTMR_ISR_0 isr_lptmr0
105 static const uart_conf_t uart_config[] = {
106  {
107  .dev = UART0,
108  .freq = CLOCK_CORECLOCK,
109  .pin_rx = GPIO_PIN(PORT_B, 16),
110  .pin_tx = GPIO_PIN(PORT_B, 17),
111  .pcr_rx = PORT_PCR_MUX(3),
112  .pcr_tx = PORT_PCR_MUX(3),
113  .irqn = UART0_RX_TX_IRQn,
114  .scgc_addr = &SIM->SCGC4,
115  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
116  .mode = UART_MODE_8N1,
117  .type = KINETIS_UART,
118  },
119 };
120 
121 #define UART_0_ISR (isr_uart0_rx_tx)
122 
123 #define UART_NUMOF ARRAY_SIZE(uart_config)
130 static const adc_conf_t adc_config[] = {
131  [ 0] = { /* PTB2 (Arduino A0) */
132  .dev = ADC0, .pin = GPIO_PIN(PORT_B, 2),
133  .chan = 12, .avg = ADC_AVG_MAX
134  },
135  [ 1] = { /* PTB3 (Arduino A1) */
136  .dev = ADC0, .pin = GPIO_PIN(PORT_B, 3),
137  .chan = 13, .avg = ADC_AVG_MAX
138  },
139  [ 2] = { /* PTB10 (Arduino A2) */
140  .dev = ADC1, .pin = GPIO_PIN(PORT_B, 10),
141  .chan = 14, .avg = ADC_AVG_MAX
142  },
143  [ 3] = { /* PTB11 (Arduino A3) */
144  .dev = ADC1, .pin = GPIO_PIN(PORT_B, 11),
145  .chan = 15, .avg = ADC_AVG_MAX
146  },
147  [ 4] = { /* PTC11 (Arduino A4) */
148  .dev = ADC1, .pin = GPIO_PIN(PORT_C, 11),
149  .chan = 7, .avg = ADC_AVG_MAX
150  },
151  [ 5] = { /* PTC10 (Arduino A5) */
152  .dev = ADC1, .pin = GPIO_PIN(PORT_C, 10),
153  .chan = 6, .avg = ADC_AVG_MAX
154  },
155  [ 6] = { /* ADC0_DP0 */
156  .dev = ADC0, .pin = GPIO_UNDEF,
157  .chan = 0, .avg = ADC_AVG_MAX
158  },
159  [ 7] = { /* ADC0_DM0 */
160  .dev = ADC0, .pin = GPIO_UNDEF,
161  .chan = 19, .avg = ADC_AVG_MAX
162  },
163  [ 8] = { /* ADC0_DP0 - ADC0_DM0 */
164  .dev = ADC0, .pin = GPIO_UNDEF,
165  .chan = (0 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX
166  },
167  [ 9] = { /* ADC1_DP0 */
168  .dev = ADC1, .pin = GPIO_UNDEF,
169  .chan = 0, .avg = ADC_AVG_MAX
170  },
171  [10] = { /* ADC1_DM0 */
172  .dev = ADC1, .pin = GPIO_UNDEF,
173  .chan = 19, .avg = ADC_AVG_MAX
174  },
175  [11] = { /* ADC1_DP0 - ADC1_DM0 */
176  .dev = ADC1, .pin = GPIO_UNDEF,
177  .chan = (0 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX
178  },
179  [12] = { /* ADC0_DP1 */
180  .dev = ADC0, .pin = GPIO_UNDEF,
181  .chan = 1, .avg = ADC_AVG_MAX
182  },
183  [13] = { /* ADC0_DM1 */
184  .dev = ADC0, .pin = GPIO_UNDEF,
185  .chan = 20, .avg = ADC_AVG_MAX
186  },
187  [14] = { /* ADC0_DP1 - ADC0_DM1 */
188  .dev = ADC0, .pin = GPIO_UNDEF,
189  .chan = (1 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX
190  },
191  [15] = { /* ADC1_DP1 */
192  .dev = ADC1, .pin = GPIO_UNDEF,
193  .chan = 1, .avg = ADC_AVG_MAX
194  },
195  [16] = { /* ADC1_DM1 */
196  .dev = ADC1, .pin = GPIO_UNDEF,
197  .chan = 20, .avg = ADC_AVG_MAX
198  },
199  [17] = { /* ADC1_DP1 - ADC1_DM1 */
200  .dev = ADC1, .pin = GPIO_UNDEF,
201  .chan = (1 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX
202  },
203  /* internal: temperature sensor */
204  /* The temperature sensor has a very high output impedance, it must
205  * not be sampled using hardware averaging, or the sampled values
206  * will be garbage */
207  [18] = {
208  .dev = ADC0, .pin = GPIO_UNDEF,
209  .chan = 26, .avg = ADC_AVG_NONE
210  },
211  /* internal: band gap */
212  /* Note: the band gap buffer uses a bit of current and is turned off
213  * by default, set PMC->REGSC |= PMC_REGSC_BGBE_MASK before reading
214  * or the input will be floating */
215  [19] = {
216  .dev = ADC0, .pin = GPIO_UNDEF,
217  .chan = 27, .avg = ADC_AVG_MAX
218  },
219 };
220 
221 #define ADC_NUMOF ARRAY_SIZE(adc_config)
222 /*
223  * K64F ADC reference settings:
224  * 0: VREFH/VREFL external pin pair
225  * 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
226  * 2-3: reserved
227  */
228 #define ADC_REF_SETTING 0
235 static const pwm_conf_t pwm_config[] = {
236  {
237  .ftm = FTM0,
238  .chan = {
239  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 6 },
240  { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
241  { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
242  { .pin = GPIO_PIN(PORT_C, 3), .af = 4, .ftm_chan = 2 }
243  },
244  .chan_numof = 4,
245  .ftm_num = 0
246  }
247 };
248 
249 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
262 static const uint32_t spi_clk_config[] = {
263  (
264  SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
265  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
266  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
267  SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
268  ),
269  (
270  SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
271  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
272  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
273  SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
274  ),
275  (
276  SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
277  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
278  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
279  SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
280  ),
281  (
282  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
283  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
284  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
285  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
286  ),
287  (
288  SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
289  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
290  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
291  SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
292  )
293 };
294 
295 static const spi_conf_t spi_config[] = {
296  {
297  .dev = SPI0,
298  .pin_miso = GPIO_PIN(PORT_D, 3),
299  .pin_mosi = GPIO_PIN(PORT_D, 2),
300  .pin_clk = GPIO_PIN(PORT_D, 1),
301  .pin_cs = {
302  GPIO_PIN(PORT_D, 0),
303  SPI_CS_UNDEF,
304  SPI_CS_UNDEF,
305  SPI_CS_UNDEF,
307  },
308  .pcr = GPIO_AF_2,
309  .simmask = SIM_SCGC6_SPI0_MASK
310  }
311 };
312 
313 #define SPI_NUMOF ARRAY_SIZE(spi_config)
320 static const i2c_conf_t i2c_config[] = {
321  {
322  .i2c = I2C0,
323  .scl_pin = GPIO_PIN(PORT_E, 24),
324  .sda_pin = GPIO_PIN(PORT_E, 25),
325  .freq = CLOCK_BUSCLOCK,
326  .speed = I2C_SPEED_FAST,
327  .irqn = I2C0_IRQn,
328  .scl_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
329  .sda_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
330  },
331 };
332 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
333 #define I2C_0_ISR (isr_i2c0)
334 #define I2C_1_ISR (isr_i2c1)
337 #ifdef __cplusplus
338 }
339 #endif
340 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
static const spi_clk_conf_t spi_clk_config[]
Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
Definition: periph_cpu.h:281
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
#define UART0
UART0 register bank.
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition: mcg.h:146
#define CLOCK_CORECLOCK
System core clock in Hz.
Definition: periph_conf.h:34
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition: periph_cpu.h:278
#define ADC_AVG_NONE
Disable hardware averaging.
Definition: periph_cpu.h:369
@ KINETIS_UART
Kinetis UART module type.
Definition: periph_cpu.h:537
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition: periph_cpu.h:293
#define ADC_AVG_MAX
Maximum hardware averaging (32 samples)
Definition: periph_cpu.h:373
ADC device configuration.
Definition: periph_cpu.h:377
ADC_TypeDef * dev
ADC device used.
Definition: periph_cpu.h:378
I2C configuration structure.
Definition: periph_cpu.h:298
I2C_Type * i2c
Pointer to hardware module registers.
Definition: periph_cpu.h:458
gpio_t pin
GPIO pin mapped to this channel.
Definition: periph_cpu.h:469
PWM device configuration.
pwm_chan_t chan[TIMER_CHANNEL_NUMOF]
channel mapping set to {GPIO_UNDEF, 0} if not used
Definition: periph_cpu.h:482
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218