periph_conf.h
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1 /*
2  * Copyright (C) 2019 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
21 /*
22  * This board provides an LSE, so enable it before including the default clock config
23  */
24 #ifndef CONFIG_BOARD_HAS_LSE
25 #define CONFIG_BOARD_HAS_LSE 1
26 #endif
27 
31 #ifndef CONFIG_BOARD_HAS_HSE
32 #define CONFIG_BOARD_HAS_HSE 1
33 #endif
34 
38 #ifndef CONFIG_CLOCK_HSE
39 #define CONFIG_CLOCK_HSE MHZ(16)
40 #endif
41 
42 #include "periph_cpu.h"
43 #include "clk_conf.h"
44 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
53 static const timer_conf_t timer_config[] = {
54  {
55  .dev = TIM3,
56  .max = 0x0000ffff,
57  .rcc_mask = RCC_APB1ENR_TIM3EN,
58  .bus = APB1,
59  .irqn = TIM3_IRQn
60  }
61 };
62 
63 #define TIMER_0_ISR (isr_tim3)
64 
65 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
72 static const uart_conf_t uart_config[] = {
73  {
74  .dev = USART1,
75  .rcc_mask = RCC_APB2ENR_USART1EN,
76  .rx_pin = GPIO_PIN(PORT_A, 10),
77  .tx_pin = GPIO_PIN(PORT_A, 9),
78  .rx_af = GPIO_AF7,
79  .tx_af = GPIO_AF7,
80  .bus = APB2,
81  .irqn = USART1_IRQn
82  },
83 };
84 
85 #define UART_0_ISR (isr_usart1)
86 
87 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
94 static const spi_conf_t spi_config[] = {
95  {
96  .dev = SPI1,
97  .mosi_pin = GPIO_PIN(PORT_A, 7),
98  .miso_pin = GPIO_PIN(PORT_A, 6),
99  .sclk_pin = GPIO_PIN(PORT_A, 5),
100  .cs_pin = SPI_CS_UNDEF,
101  .mosi_af = GPIO_AF5,
102  .miso_af = GPIO_AF5,
103  .sclk_af = GPIO_AF5,
104  .cs_af = GPIO_AF5,
105  .rccmask = RCC_APB2ENR_SPI1EN,
106  .apbbus = APB2
107  },
108  {
109  .dev = SPI2,
110  .mosi_pin = GPIO_PIN(PORT_B, 14),
111  .miso_pin = GPIO_PIN(PORT_B, 15),
112  .sclk_pin = GPIO_PIN(PORT_B, 13),
113  .cs_pin = GPIO_PIN(PORT_B, 12),
114  .mosi_af = GPIO_AF5,
115  .miso_af = GPIO_AF5,
116  .sclk_af = GPIO_AF5,
117  .cs_af = GPIO_AF5,
118  .rccmask = RCC_APB1ENR_SPI2EN,
119  .apbbus = APB1
120  }
121 };
122 
123 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
130 static const i2c_conf_t i2c_config[] = {
131  {
132  .dev = I2C1,
133  .speed = I2C_SPEED_NORMAL,
134  .scl_pin = GPIO_PIN(PORT_B, 8),
135  .sda_pin = GPIO_PIN(PORT_B, 9),
136  .scl_af = GPIO_AF4,
137  .sda_af = GPIO_AF4,
138  .bus = APB1,
139  .rcc_mask = RCC_APB1ENR_I2C1EN,
140  .clk = CLOCK_APB1,
141  .irqn = I2C1_EV_IRQn
142  }
143 };
144 
145 #define I2C_0_ISR isr_i2c1_ev
146 
147 #define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
154 static const adc_conf_t adc_config[] = {
155  { GPIO_PIN(PORT_A, 0), 0 }, /* P14 */
156  { GPIO_PIN(PORT_A, 1), 1 }, /* P15 */
157  { GPIO_PIN(PORT_A, 3), 3 }, /* P17 */
158  /* ADC Temperature channel */
159  { GPIO_UNDEF, 16 },
160  /* ADC VREF channel */
161  { GPIO_UNDEF, 17 },
162 };
163 
164 #define ADC_NUMOF ARRAY_SIZE(adc_config)
167 #ifdef __cplusplus
168 }
169 #endif
170 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
#define CLOCK_APB1
Half AHB clock.
ADC device configuration.
Definition: periph_cpu.h:377
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218