periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universität Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
22 /* HSE available on this board */
23 #ifndef CONFIG_BOARD_HAS_HSE
24 #define CONFIG_BOARD_HAS_HSE 1
25 #endif
26 
27 /* This board provides an LSE */
28 #ifndef CONFIG_BOARD_HAS_LSE
29 #define CONFIG_BOARD_HAS_LSE 1
30 #endif
31 
32 #include "periph_cpu.h"
33 #include "clk_conf.h"
34 #include "cfg_i2c1_pb8_pb9.h"
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
44 static const timer_conf_t timer_config[] = {
45  {
46  .dev = TIM1,
47  .max = 0x0000ffff,
48  .rcc_mask = RCC_APB2ENR_TIM1EN,
49  .bus = APB2,
50  .irqn = TIM1_CC_IRQn
51  }
52 };
53 
54 #define TIMER_0_ISR isr_tim1_cc
55 
56 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
63 static const uart_conf_t uart_config[] = {
64  {
65  .dev = USART2,
66  .rcc_mask = RCC_APB1ENR_USART2EN,
67  .rx_pin = GPIO_PIN(PORT_A, 3),
68  .tx_pin = GPIO_PIN(PORT_A, 2),
69  .rx_af = GPIO_AF1,
70  .tx_af = GPIO_AF1,
71  .bus = APB1,
72  .irqn = USART2_IRQn
73  },
74  {
75  .dev = USART1,
76  .rcc_mask = RCC_APB2ENR_USART1EN,
77  .rx_pin = GPIO_PIN(PORT_A, 10),
78  .tx_pin = GPIO_PIN(PORT_A, 9),
79  .rx_af = GPIO_AF1,
80  .tx_af = GPIO_AF1,
81  .bus = APB2,
82  .irqn = USART1_IRQn
83  },
84  {
85  .dev = USART3,
86  .rcc_mask = RCC_APB1ENR_USART3EN,
87  .rx_pin = GPIO_PIN(PORT_C, 11),
88  .tx_pin = GPIO_PIN(PORT_C, 10),
89  .rx_af = GPIO_AF1,
90  .tx_af = GPIO_AF1,
91  .bus = APB1,
92  .irqn = USART3_8_IRQn
93  }
94 };
95 
96 #define UART_0_ISR (isr_usart2)
97 #define UART_1_ISR (isr_usart1)
98 #define UART_2_ISR (isr_usart3_8)
99 
100 #define UART_NUMOF ARRAY_SIZE(uart_config)
107 static const pwm_conf_t pwm_config[] = {
108  {
109  .dev = TIM2,
110  .rcc_mask = RCC_APB1ENR_TIM2EN,
111  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
112  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
113  { .pin = GPIO_PIN(PORT_B, 11) , .cc_chan = 3 },
114  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
115  .af = GPIO_AF2,
116  .bus = APB1
117  },
118  {
119  .dev = TIM3,
120  .rcc_mask = RCC_APB1ENR_TIM3EN,
121  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
122  { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1 },
123  { .pin = GPIO_UNDEF, .cc_chan = 0 },
124  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
125  .af = GPIO_AF1,
126  .bus = APB1
127  },
128  {
129  .dev = TIM15,
130  .rcc_mask = RCC_APB2ENR_TIM15EN,
131  .chan = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0 },
132  { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1 },
133  { .pin = GPIO_UNDEF, .cc_chan = 0 },
134  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
135  .af = GPIO_AF1,
136  .bus = APB2
137  }
138 };
139 
140 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
147 static const spi_conf_t spi_config[] = {
148  {
149  .dev = SPI1,
150  .mosi_pin = GPIO_PIN(PORT_A, 7),
151  .miso_pin = GPIO_PIN(PORT_A, 6),
152  .sclk_pin = GPIO_PIN(PORT_A, 5),
153  .cs_pin = GPIO_PIN(PORT_A, 4),
154  .mosi_af = GPIO_AF0,
155  .miso_af = GPIO_AF0,
156  .sclk_af = GPIO_AF0,
157  .cs_af = GPIO_AF0,
158  .rccmask = RCC_APB2ENR_SPI1EN,
159  .apbbus = APB2
160  },
161  {
162  .dev = SPI2,
163  .mosi_pin = GPIO_PIN(PORT_B, 15),
164  .miso_pin = GPIO_PIN(PORT_B, 14),
165  .sclk_pin = GPIO_PIN(PORT_B, 13),
166  .cs_pin = GPIO_PIN(PORT_B, 12),
167  .mosi_af = GPIO_AF0,
168  .miso_af = GPIO_AF0,
169  .sclk_af = GPIO_AF0,
170  .cs_af = GPIO_AF0,
171  .rccmask = RCC_APB1ENR_SPI2EN,
172  .apbbus = APB1
173  },
174 };
175 
176 #define SPI_NUMOF ARRAY_SIZE(spi_config)
183 static const adc_conf_t adc_config[] = {
184  { GPIO_PIN(PORT_A, 0), 0 },
185  { GPIO_PIN(PORT_A, 1), 1 },
186  { GPIO_PIN(PORT_A, 4), 4 },
187  { GPIO_PIN(PORT_B, 0), 8 },
188  { GPIO_PIN(PORT_C, 1), 11 },
189  { GPIO_PIN(PORT_C, 0), 10 },
190  { GPIO_UNDEF, 18 }, /* VBAT */
191 };
192 
193 #define VBAT_ADC ADC_LINE(6)
194 #define ADC_NUMOF ARRAY_SIZE(adc_config)
197 #ifdef __cplusplus
198 }
199 #endif
200 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
Common configuration for STM32 I2C.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF0
use alternate function 0
Definition: cpu_gpio.h:101
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218