periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
21 #include "periph_cpu.h"
22 #include "cfg_clock_default.h"
23 #include "cfg_rtc_default.h"
24 #include "cfg_rtt_default.h"
25 #include "cfg_spi_default.h"
26 #include "cfg_timer_default.h"
27 #include "cfg_usbdev_default.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
37 static const uart_conf_t uart_config[] = {
38  {
39  .dev = &SERCOM5->USART,
40  .rx_pin = GPIO_PIN(PB,31), /* D0, RX Pin */
41  .tx_pin = GPIO_PIN(PB,30), /* D1, TX Pin */
42 #ifdef MODULE_PERIPH_UART_HW_FC
43  .rts_pin = GPIO_UNDEF,
44  .cts_pin = GPIO_UNDEF,
45 #endif
46  .mux = GPIO_MUX_D,
47  .rx_pad = UART_PAD_RX_1,
48  .tx_pad = UART_PAD_TX_0_RTS_2_CTS_3,
49  .flags = UART_FLAG_NONE,
50  .gclk_src = SAM0_GCLK_MAIN,
51  },
52  {
53  .dev = &SERCOM4->USART,
54  .rx_pin = GPIO_PIN(PB,13),
55  .tx_pin = GPIO_PIN(PB,14),
56 #ifdef MODULE_PERIPH_UART_HW_FC
57  .rts_pin = GPIO_UNDEF,
58  .cts_pin = GPIO_UNDEF,
59 #endif
60  .mux = GPIO_MUX_C,
61  .rx_pad = UART_PAD_RX_1,
62  .tx_pad = UART_PAD_TX_2,
63  .flags = UART_FLAG_NONE,
64  .gclk_src = SAM0_GCLK_MAIN,
65  },
66  { /* Connected to RN2483 */
67  .dev = &SERCOM0->USART,
68  .rx_pin = GPIO_PIN(PA,5),
69  .tx_pin = GPIO_PIN(PA,6),
70 #ifdef MODULE_PERIPH_UART_HW_FC
71  .rts_pin = GPIO_UNDEF,
72  .cts_pin = GPIO_UNDEF,
73 #endif
74  .mux = GPIO_MUX_D,
75  .rx_pad = UART_PAD_RX_1,
76  .tx_pad = UART_PAD_TX_2,
77  .flags = UART_FLAG_NONE,
78  .gclk_src = SAM0_GCLK_MAIN,
79  },
80 };
81 
82 /* interrupt function name mapping */
83 #define UART_0_ISR isr_sercom5
84 #define UART_1_ISR isr_sercom4
85 #define UART_2_ISR isr_sercom0
86 
87 #define UART_NUMOF ARRAY_SIZE(uart_config)
95 /* ADC Default values */
96 #define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
97 
98 #define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
99 #define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_DIV2
100 #define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
101 
102 static const adc_conf_chan_t adc_channels[] = {
103  /* port, pin, muxpos */
104  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB00 }, /* A0 */
105  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB01 }, /* A1 */
106  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB02 }, /* A2 */
107  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB03 }, /* A3 */
108  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA08 }, /* A4 */
109  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA09 }, /* A5 */
110  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA04 }, /* A6 (temperature) */
111  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA10 }, /* A7 */
112  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA11 }, /* A8 */
113  { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB05 }, /* BATVOLT */
114 };
115 
116 #define ADC_NUMOF ARRAY_SIZE(adc_channels)
123 static const i2c_conf_t i2c_config[] = {
124  {
125  .dev = &(SERCOM1->I2CM),
126  .speed = I2C_SPEED_NORMAL,
127  .scl_pin = GPIO_PIN(PA, 17),
128  .sda_pin = GPIO_PIN(PA, 16),
129  .mux = GPIO_MUX_C,
130  .gclk_src = SAM0_GCLK_MAIN,
131  .flags = I2C_FLAG_NONE,
132  },
133  {
134  .dev = &(SERCOM2->I2CM),
135  .speed = I2C_SPEED_NORMAL,
136  .scl_pin = GPIO_PIN(PA, 9),
137  .sda_pin = GPIO_PIN(PA, 8),
138  .mux = GPIO_MUX_C,
139  .gclk_src = SAM0_GCLK_MAIN,
140  .flags = I2C_FLAG_NONE
141  }
142 };
143 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
146 #ifdef __cplusplus
147 }
148 #endif
149 
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
Default RTC configuration for SODAQ boards.
static const gpio_t adc_channels[]
Static array with declared ADC channels.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
@ UART_PAD_RX_1
select pad 1
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0_RTS_2_CTS_3
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
@ UART_PAD_TX_2
select pad 2
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
#define ADC_INPUTCTRL_MUXPOS_PB02
Alias for PIN10.
Definition: periph_cpu.h:128
#define ADC_INPUTCTRL_MUXPOS_PA10
Alias for PIN18.
Definition: periph_cpu.h:136
#define ADC_INPUTCTRL_MUXPOS_PA11
Alias for PIN19.
Definition: periph_cpu.h:137
#define ADC_INPUTCTRL_MUXPOS_PA08
Alias for PIN16.
Definition: periph_cpu.h:134
#define ADC_INPUTCTRL_MUXPOS_PA09
Alias for PIN17.
Definition: periph_cpu.h:135
#define ADC_INPUTCTRL_MUXPOS_PB01
Alias for PIN9.
Definition: periph_cpu.h:127
#define ADC_INPUTCTRL_MUXPOS_PA04
Alias for PIN4.
Definition: periph_cpu.h:122
#define ADC_INPUTCTRL_MUXPOS_PB03
Alias for PIN11.
Definition: periph_cpu.h:129
#define ADC_INPUTCTRL_MUXPOS_PB05
Alias for PIN13.
Definition: periph_cpu.h:131
#define ADC_INPUTCTRL_MUXPOS_PB00
Alias for PIN8.
Definition: periph_cpu.h:126
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition: periph_cpu.h:73
ADC Channel Configuration.
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218