cpu_conf.h
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1 /*
2  * Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
9 #pragma once
10 
21 #include "vendor/gd32vf103_core.h"
22 #include "cpu_conf_common.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 #define CLIC_NUM_INTERRUPTS (ECLIC_NUM_INTERRUPTS)
29 #define CLIC_BASE_ADDR (ECLIC_CTRL_ADDR)
30 #define CPU_DEFAULT_IRQ_PRIO (0xFF)
31 
35 #define HAVE_CSR_MIE (0)
36 
41 #define FLASHPAGE_SIZE (1024U)
42 #define FLASHPAGE_NUMOF (128U)
43 #define FLASHPAGE_WRITE_BLOCK_SIZE (2U)
44 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
45 #define CPU_FLASH_BASE 0x08000000
51 typedef enum {
59  SWJ_CFG_NO_NJTRST = 1U << AFIO_PCF0_SWJ_CFG_Pos,
63  SWJ_CFG_NO_JTAG = 4U << AFIO_PCF0_SWJ_CFG_Pos,
65 
66 #ifndef CONFIG_AFIO_PCF0_SWJ_CFG
73 #define CONFIG_AFIO_PCF0_SWJ_CFG SWJ_CFG_NO_NJTRST
74 #endif
75 
76 #ifdef __cplusplus
77 }
78 #endif
79 
afio_pcf0_swj_cfg_t
Possible values of the SWJ_CFG field in the AFIO->PCF0 register.
Definition: cpu_conf.h:51
@ SWJ_CFG_NO_NJTRST
JTAG enabled, but NJTRST disabled and pin PB4 usable as GPIO.
Definition: cpu_conf.h:59
@ SWJ_CFG_FULL_JTAG
Full JTAG interface (reset value)
Definition: cpu_conf.h:55
@ SWJ_CFG_NO_JTAG
JTAG disabled, all debug pins usable as GPIOs.
Definition: cpu_conf.h:63